Datasheet

LM12L458
SNAS085B –JULY 1999–REVISED MARCH 2013 www.ti.com
Timing Diagrams
V
A
+ = V
D
+ = +3.3V, t
R
= t
F
= 3 ns, C
L
= 100 pF for the INT, DMARQ, D0–D15 outputs.
Figure 28. Multiplexed Data Bus
1, 3: CS or Address valid to ALE low set-up time. 11: WR pulse width
2, 4: CS or Address valid to ALE low hold time. 12: WR high to next ALE high
5: ALE pulse width 13: WR high to next WR or RD low
6: RD high to next ALE high 14: Data valid to WR high set-up time
7: ALE low to RD low 15: Data valid to WR high hold time
8: RD pulse width 16: RD low to data bus out of TRI-STATE
9: RD high to next RD or WR low 17: RD high to TRI-STATE
10: ALE low to WR low 18: RD low to data valid (access time)
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