Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
CONVERTER AC CHARACTERISTICS
(1) (2) (3) (4)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A
+ = V
D
+ = 5V, V
REF+
= 5V, V
REF−
= 0V, 12-
bit + sign conversion mode, f
CLK
= 8.0 MHz (LM12H458) or f
CLK
= 5.0 MHz (LM12454/8), R
S
= 25Ω, source impedance for
V
REF+
and V
REF−
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
Symbol Parameter Conditions Typical
(5)
Limits
(6)
Units
%
Clock Duty Cycle 50 40 % (min)
60 % (max)
13-Bit Resolution, Sequencer State
44 (t
CLK
) 44 (t
CLK
) + 50 ns (max)
S5 (Figure 45)
t
C
Conversion Time
9-Bit Resolution, Sequencer State S5
21 (t
CLK
) 21 (t
CLK
) + 50 ns (max)
(Figure 45)
Sequencer State S7 (Figure 45) Built-
9 (t
CLK
) 9 (t
CLK
) + 50 ns (max)
in minimum for 13-Bits
t
A
Acquisition Time
Built-in minimum for 9-Bits and
2 (t
CLK
) 2 (t
CLK
) + 50 ns (max)
“Watchdog” mode
t
Z
Auto-Zero Time Sequencer State S2 (Figure 45) 76 (t
CLK
) 76 (t
CLK
) + 50 ns (max)
t
CAL
4944 (t
CLK
) + 50
Full Calibration Time Sequencer State S2 (Figure 45) 4944 (t
CLK
) (max)
ns
89 88 kHz (min)
Throughput Rate
(7)
LM12H458 142 140 kHz (min)
“Watchdog” Mode Comparison Time Sequencer States S6, S4, and S5
t
WD
11 (t
CLK
) 11 (t
CLK
) + 50 ns (max)
(Figure 45)
V
IN
= ±5V
f
IN
= 1 kHz 77.5 dB
DSNR Differential Signal-to-Noise Ratio
f
IN
= 20 kHz 75.2 dB
f
IN
= 40 kHz 74.7 dB
V
IN
= 5 V
p-p
f
IN
= 1 kHz 69.8 dB
SESNR Single-Ended Signal-to-Noise Ratio
f
IN
= 20 kHz 69.2 dB
f
IN
= 40 kHz 66.6 dB
V
IN
= ±5V
f
IN
= 1 kHz 76.9 dB
Differential Signal-to-Noise +
DSINAD
Distortion Ratio
f
IN
= 20 kHz 73.9 dB
f
IN
= 40 kHz 70.7 dB
V
IN
= 5 V
p-p
f
IN
= 1 kHz 69.4 dB
Single-Ended Signal-to-Noise +
SESINAD
Distortion Ratio
f
IN
= 20 kHz 68.3 dB
f
IN
= 40 kHz 65.7 dB
(1) Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above
V
A
+ or 5V below GND will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these
diodes are forward biased by more than 100 mV. As an example, if V
A
+ is 4.5 V
DC
, full-scale input voltage must be ≤4.6 V
DC
to ensure
accurate conversions. See Figure 3
(2) V
A
+ and V
D
+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+
pin to
assure conversion/comparison accuracy.
(3) Accuracy is ensured when operating at f
CLK
= 5 MHz for the LM12454/8 and f
CLK
= 8 MHz for the LM12H458.
(4) With the test condition for V
REF
(V
REF+
− V
REF−
) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.
(5) Typical figures are at T
A
= 25°C and represent most likely parametric norm.
(6) Limits are to AOQL (Average Output Quality Level).
(7) The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock
cycles) and 5 (44 clock cycles) are used (see Figure 45). One additional clock cycle is used to read the conversion result stored in the
FIFO, for a total of 56 clock cycles per conversion. The Throughput Rate is f
CLK
(MHz)/N, where N is the number of clock
cycles/conversion.
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Product Folder Links: LM12454 LM12458 LM12H458