Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a “1”, state 2 is 76 clock
cycles long. If the Configuration register's bit 3 is set to a “1”, state 2 is 4944 clock cycles long.
State 3: Run the internal 16-bit Timer. The number of clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is found by using the expression below
32T + 2 (3)
where 0 ≤ T ≤ 2
16
−1.
State 7: Run the acquisition delay and read Limit #1's value if needed. The number of clock cycles for 12-bit +
sign mode varies according to
9 + 2D (4)
where D is the user-programmable 4-bit value stored in bits 12–15 of Instruction RAM “00” and is limited to 0 ≤ D
≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog” mode varies according to
2 + 2D (5)
where D is the user-programmable 4-bit value stored in bits 12–15 of Instruction RAM “00” and is limited to 0 ≤ D
≤ 15.
State 6: Perform first comparison. This state is 5 clock cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison. This state takes 44 clock cycles when using the 12-bit +
sign mode or 21 clock cycles when using the 8-bit + sign mode. The “watchdog” mode takes 5 clock cycles.
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Product Folder Links: LM12454 LM12458 LM12H458