Datasheet

LM12454, LM12458, LM12H458
SNAS079A –MAY 2004–REVISED FEBRUARY 2006 www.ti.com
The completion of a full auto-zero and linearity self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters an instruction that has its Pause bit (Bit 1 in Instruction
RAM “00”) set to “1”.
The LM12(H)454/8 issues Interrupt 6 whenever it senses that its power supply voltage is dropping below 4V
(typ). This interrupt indicates the potential corruption of data returned by the LM12(H)454/8.
Interrupt 7 is issued after a short delay (10 ms typ) while the LM12(H)454/8 returns from Standby mode to active
operation using the Configuration register's Bit 4. This short delay allows the internal analog circuitry to settle
sufficiently, ensuring accurate conversion results.
INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001 (A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has
READ/WRITE capability. An individual interrupt's ability to produce an external interrupt at pin 31 (INT) is
accomplished by placing a “1” in the appropriate bit location. Any of the internal interrupt-producing operations
will set their corresponding bits to “1” in the Interrupt Status register regardless of the state of the associated bit
in the Interrupt Enable register. See Section 2.3 for more information about each of the eight internal interrupts.
Bit 0 enables an external interrupt when an internal “watchdog” comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has reached the address stored in Bits 8–10 of the
Interrupt Enable register.
Bit 2 enables an external interrupt when the Conversion FIFO's limit, stored in Bits 11–15 of the Interrupt Enable
register, has been reached.
Bit 3 enables an external interrupt when the single-sample auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and linearity self-calibration has been completed.
Bit 5 enables an external interrupt when an internal Pause interrupt has been generated.
Bit 6 enables an external interrupt when a low power supply condition (V
A
+ < 4V) has generated an internal
interrupt.
Bit 7 enables an external interrupt when the LM12(H)454/8 return from power-down to active mode.
Bits 8 – 10 form the storage location of the user-programmable value against which the Sequencer's address is
compared. When the Sequencer reaches an address that is equal to the value stored in Bits 8–10, an internal
interrupt is generated and appears in Bit 1 of the Interrupt Status register. If Bit 1 of the Interrupt Enable register
is set to “1”, an external interrupt will appear at pin 31 (INT).
The value stored in bits 8–10 ranges from 000 to 111, representing 0 to 7 instructions stored in the Instruction
RAM. After the Instruction RAM has been programmed and the RESET bit is set to “1”, the Sequencer is started
by placing a “1” in the Configuration register's START bit. Setting the INT 1 trigger value to 000 does not
generate an INT 1 the first time the Sequencer retrieves and decodes Instruction 000. The Sequencer
generates INT 1 (by placing a “1” in the Interrupt Status register's Bit 1) the second time and after the
Sequencer encounters Instruction 000. It is important to remember that the Sequencer continues to operate even
if an Instruction interrupt (INT 1) is internally or externally generated. The only mechanisms that stop the
Sequencer are an instruction with the PAUSE bit set to “1” (halts before instruction execution), placing a “0” in
the Configuration register's START bit, or placing a “1” in the Configuration register's RESET bit.
Bits 11–15 hold the number of conversions that must be stored in the Conversion FIFO in order to generate an
internal interrupt. This internal interrupt appears in Bit 2 of the Interrupt Status register. If Bit 2 of the Interrupt
Enable register is set to “1”, an external interrupt will appear at pin 31 (INT).
Other Registers and Functions
INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1). The
corresponding flag in the Interrupt Status register goes high (“1”) any time that an interrupt condition takes place,
whether an interrupt is enabled or disabled in the Interrupt Enable register. Any of the active (“1”) Interrupt Status
register flags are reset to “0” whenever this register is read or a device reset is issued (see Bit 1 in the
Configuration Register).
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