Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
Bit 11 is the Diagnostic bit and is available only in the LM12(H)458. It can be activated by setting it to a “1” (the
Test bit must be reset to a “0”). The Diagnostic mode, along with a correctly chosen instruction, allows
verification that the LM12(H)458's ADC is performing correctly. When activated, the inverting and non-inverting
inputs are connected as shown in Table 3. As an example, an instruction with “001” for both V
IN+
and V
IN−
while
using the Diagnostic mode typically results in a full-scale output.
INTERRUPTS
The LM12454 and LM12(H)458 have eight possible interrupts, all with the same priority. Any of these interrupts
will cause a hardware interrupt to appear on the INT pin (31) if they are not masked (by the Interrupt Enable
register). The Interrupt Status register is then read to determine which of the eight interrupts has been issued.
Table 3. LM12(H)458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
Channel Normal Mode Diagnostic Mode
Selection
V
IN+
V
IN−
V
IN+
V
IN−
Data
000 IN0 GND V
REFOUT
GND
001 IN1 IN1 V
REF+
V
REF−
010 IN2 IN2 IN2 IN2
011 IN3 IN3 IN3 IN3
100 IN4 IN4 IN4 IN4
101 IN5 IN5 IN5 IN5
110 IN6 IN6 IN6 IN6
111 IN7 IN7 IN7 IN7
Table 4. LM12454 Input Multiplexer
Channel Configuration
Channel Selection Data MUX+ MUX−
000 IN0 GND
001 IN1 IN1
010 IN2 IN2
011 IN3 IN3
1XX OPEN OPEN
NOTE: The LM12(H)454 is no longer available. Information shown for reference only.
The Interrupt Status register, 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1) must be cleared by reading it
after writing to the Interrupt Enable register. This removes any spurious interrupts on the INT pin generated
during an Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage on a selected multiplexer channel crosses a limit
while the LM12(H)454/8 are operating in the “watchdog” comparison mode. Two sequential comparisons are
made when the LM12(H)454/8 are executing a “watchdog” instruction. Depending on the logic state of Bit 9 in
the Instruction RAM's second and third sections, an interrupt will be generated either when the input signal's
magnitude is greater than or less than the programmable limits. (See the Instruction RAM, Bit 9 description.) The
Limit Status register will indicate which preprogrammed limit, #1 or #2 and which instruction was executing when
the limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the instruction counter value specified in the Interrupt
Enable register's bits 8–10. This flag appears before the instruction's execution.
Interrupt 2 is activated when the Conversion FIFO holds a number of conversions equal to the programmable
value stored in the Interrupt Enable register's Bits 11–15. This value ranges from 0001 to 1111, representing 1 to
31 conversions stored in the FIFO. A user-programmed value of 0000 has no meaning. See Section 3.0 for more
FIFO information.
The completion of the short, single-sample auto-zero calibration generates Interrupt 3.
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Product Folder Links: LM12454 LM12458 LM12H458