Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
Bits 12–15 are used to store the user-programmable acquisition time. The Sequencer keeps the internal S/H in
the acquisition mode for a fixed number of clock cycles (nine clock cycles, for 12-bit + sign conversions and two
clock cycles for 8-bit + sign conversions or “watchdog” comparisons) plus a variable number of clock cycles
equal to twice the value stored in Bits 12–15. Thus, the S/H's acquisition time is (9 + 2D) clock cycles for 12-bit +
sign conversions and (2 + 2D) clock cycles for 8-bit + sign conversions or “watchdog” comparisons, where D is
the value stored in Bits 12–15. The minimum acquisition time compensates for the typical internal multiplexer
series resistance of 2 kΩ, and any additional delay created by Bits 12–15 compensates for source resistances
greater than 60Ω (100Ω). (For this acquisition time discussion, numbers in ( ) are shown for the LM12(H)454/8
operating at 5 MHz.) The necessary acquisition time is determined by the source impedance at the multiplexer
input. If the source resistance (R
S
) < 60Ω (100Ω) and the clock frequency is 8 MHz, the value stored in bits
12–15 (D) can be 0000. If R
S
> 60Ω (100Ω), the following equations determine the value that should be stored in
bits 12–15.
D = 0.45 x R
S
x f
CLK
(1)
for 12-bits + sign
D = 0.36 x R
S
x f
CLK
(2)
for 8-bits + sign and “watchdog”
R
S
is in kΩ and f
CLK
is in MHz. Round the result to the next higher integer value. If D is greater than 15, it is
advisable to lower the source impedance by using an analog buffer between the signal source and the
LM12(H)458's multiplexer inputs. The value of D can also be used to compensate for the settling or response
time of external processing circuits connected between the LM12454's MUXOUT and S/H IN pins.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a “01” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #1. When Bit 11 of Instruction RAM “00” is set to a “1”, the LM12(H)454/8
performs a “watchdog” comparison of the sampled analog input signal with the limit #1 value first, followed by a
comparison of the same sampled analog input signal with the value found in limit #2 (Instruction RAM “10”).
Bit 8 holds limit #1's sign.
Bit 9's state determines the limit condition that generates a “watchdog” interrupt. A “1” causes a voltage greater
than limit #1 to generate an interrupt, while a “0” causes a voltage less than limit #1 to generate an interrupt.
Bits 10–15 are not used.
Instruction RAM “10”
The third Instruction RAM section is selected by placing a “10” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #2. When Bit 11 of Instruction RAM “00” is set to a “1”, the LM12(H)454/8
performs a “watchdog” comparison of the sampled analog input signal with the limit #1 value first (Instruction
RAM “01”), followed by a comparison of the same sampled analog input signal with the value found in limit #2.
Bit 8 holds limit #2's sign.
Bit 9 's state determines the limit condition that generates a “watchdog” interrupt. A “1” causes a voltage greater
than limit #2 to generate an interrupt, while a “0” causes a voltage less than limit #2 to generate an interrupt.
Bits 10–15 are not used.
CONFIGURATION REGISTER
The Configuration register, 1000 (A4–A1, BW = 0) or 1000x (A4–A0, BW = 1) is a 16-bit control register with
read/write capability. It acts as the LM12454's and LM12(H)458's “control panel” holding global information as
well as start/stop, reset, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indication of the Sequencer's status. A “0” indicates that
the Sequencer is stopped and waiting to execute the next instruction. A “1” shows that the Sequencer is running.
Writing a “0” halts the Sequencer when the current instruction has finished execution. The next instruction to be
executed is pointed to by the instruction pointer found in the status register. A “1” restarts the Sequencer with the
instruction currently pointed to by the instruction pointer. (See Bits 8–10 in the Interrupt Status register.)
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