Datasheet

LM12454, LM12458, LM12H458
SNAS079A –MAY 2004–REVISED FEBRUARY 2006 www.ti.com
Table 2. LM12(H)454/8 Memory Map for 8-Bit Wide Data Bus (BW = “1” and Test Bit = “0”)
A4 A3 A2 A1 A0 Purpose Type D7 D6 D5 D4 D3 D2 D1 D0
0 0 0
V
IN−
(MUXOUT−) V
IN+
(MUXOUT+)
0 to 0 R/W Pause Loop
Instruction
(1) (1)
RAM
1 1 1
(RAM
0 0 0
Pointer =
00)
0 to 1 R/W Acquisition Time Watch- dog 8/12 Timer Sync
1 1 1
0 0 0
R/W Comparison Limit #1
Instruction RAM
0 to 0
(RAM Pointer = 01)
1 1 1 R/W Don't Care >/< Sign
0 0 0
0 to 1 R/W Don't Care >/< Sign
1 1 1
0 0 0
0 to 0 R/W Comparison Limit #2
Instruction
RAM
1 1 1
(RAM
0 0 0
Pointer =
10)
0 to 1 R/W Don't Care >/< Sign
1 1 1
1 0 0 0 0 R/W I/O Sel Auto Zero
ec
Chan Mask Stand- by Full Cal Auto- Zero Reset Start
Configuration
Register
1 0 0 0 1 R/W Don't Care DIAG
(2)
Test = 0 RAM Pointer
1 0 0 1 0 Interrupt R/W INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
Enable
1 0 0 1 1 R/W Number of Conversions in Conversion FIFO to Generate INT2 Sequencer Address to Generate INT1
Register
1 0 1 0 0 Interrupt R INST7 INST6 INST5 INST4 INST3 INST2 INST1 INST0
Status
1 0 1 0 1 R Actual Number of Conversions Results in Conversion FIFO Address of Sequencer Instruction being Executed
Register
1 0 1 1 0 R/W Timer Preset: Low Byte
Timer
Register
1 0 1 1 1 R/W Timer Preset: High Byte
1 1 0 0 0 R Conversion Data: LSBs
Conversion
FIFO
1 1 0 0 1 R Address or Sign Sign Conversion Data: MSBs
1 1 0 1 0 R Limit #1 Status
Limit Status
Register
1 1 0 1 1 R Limit #2 Status
(1) LM12454 (Refer toTable 4).
(2) LM12(H)458 only. Must be set to “0” for the LM12454.
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