Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
Table 1. LM12(H)454/8 Memory Map for 16-Bit Wide Data Bus (BW = “0”, Test Bit = “0” and A0 = Don't Care)
A4 A3 A2 A1 Purpo Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
se
0 0 0 Instruc
tion
0 to
RAM Watch
R/W Acquisition Time 8/12 Timer Sync V
IN−
(MUXOUT−)
(1)
V
IN+
(MUXOUT+)
(1)
Pause Loop
(RAM - dog
1 1 1
Pointe
r = 00)
0 0 0 Instruc
tion
0 to
RAM
R/W Don't Care >/< Sign Limit #1
1 1 1
(RAM
Pointe
r = 01)
0 0 0 Instruc
tion
0 to
RAM
R/W Don't Care >/< Sign Limit #2
1 1 1
(RAM
Pointe
r = 10)
Config
uration DIAG * Test = Auto Char Stand- Full Auto-
1 0 0 0 R/W Don't Care RAM Pointer i/O Sel Reset Start
Regist
(2)
0 Zero
ec
Mask by CAL Zero
er
Interru
pt
Number of Conversions in Conversion Sequencer Address to
1 0 0 1 Enable R/W INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
FIFO to Generate INT2 Generate INT1
Regist
er
Interru
pt Address of Sequencer
Actual Number of Conversion Results in
1 0 1 0 Status R Instruction being INST7 INST6 INST5 INST4 INST3 INST2 INST1 INST0
Conversion FIFO
Regist Executed
er
Timer R/W
1 0 1 1 Regist Timer Preset High Byte Timer Preset Low Byte
er
Conve
1 1 0 0 rsion R Address or Sign Sign Conversion Data: MSBs Conversion Data: LSBs
FIFO
Limit
Status
1 1 0 1 R Limit #2: Status Limit #1: Status
Regist
er
(1) LM12454 (Refer to Table 4).
(2) LM12(H)458 only. Must be set to “0” for the LM12454.
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Product Folder Links: LM12454 LM12458 LM12H458