Datasheet

LM12454, LM12458, LM12H458
SNAS079A –MAY 2004–REVISED FEBRUARY 2006 www.ti.com
The three sections in the Instruction RAM are selected by the Configuration Register's 2-bit “RAM Pointer”, bits
D8 and D9. The first 16-bit Instruction RAM section is selected with the RAM Pointer equal to “00”. This section
provides multiplexer channel selection, as well as resolution, acquisition time, etc. The second 16-bit section
holds “watchdog” limit #1, its sign, and an indicator that shows that an interrupt can be generated if the input
signal is greater or less than the programmed limit. The third 16-bit section holds “watchdog” limit #2, its sign,
and an indicator that shows that an interrupt can be generated if the input signal is greater or less than the
programmed limit.
Instruction RAM “00”
Bit 0 is the LOOP bit. It indicates the last instruction to be executed in any instruction sequence when it is set to
a “1”. The next instruction to be executed will be instruction 0.
Bit 1 is the PAUSE bit. This controls the Sequencer's operation. When the PAUSE bit is set (“1”), the Sequencer
will stop after reading the current instruction and before executing it, and the start bit in the Configuration register
is automatically reset to a “0”. Setting the PAUSE also causes an interrupt to be issued. The Sequencer is
restarted by placing a “1” in the Configuration register's Bit 0 (Start bit).
After the Instruction RAM has been programmed and the RESET bit is set to “1”, the Sequencer retrieves
Instruction 000, decodes it, and waits for a “1” to be placed in the Configuration's START bit. The START bit
value of “0” “overrides” the action of Instruction 000's PAUSE bit when the Sequencer is started. Once started,
the Sequencer executes Instruction 000 and retrieves, decodes, and executes each of the remaining instructions.
No PAUSE Interrupt (INT 5) is generated the first time the Sequencer executes Instruction 000 having a PAUSE
bit set to “1”. When the Sequencer encounters a LOOP bit or completes all eight instructions, Instruction 000 is
retrieved and decoded. A set PAUSE bit in Instruction 000 now halts the Sequencer before the instruction is
executed.
Bits 2–4 select which of the eight input channels (“000” to “111” for IN0–IN7) will be configured as non-inverting
inputs to the LM12(H)458's ADC. (See Table 3.) They select which of the four input channels (“000” to “011” for
IN0–IN4) will be configured as non-inverting inputs to the LM12454's ADC. (See Table 4.)
Bits 5–7 select which of the seven input channels (“001” to “111” for IN1 to IN7) will be configured as inverting
inputs to the LM12(H)458's ADC. (See Table 3.) They select which of the three input channels (“001” to “011” for
IN1–IN4) will be configured as inverting inputs to the LM12454's ADC. (See Table 4.) Fully differential operation
is created by selecting two multiplexer channels, one operating in the non-inverting mode and the other operating
in the inverting mode. A code of “000” selects ground as the inverting input for single ended operation.
Bit 8 is the SYNC bit. Setting Bit 8 to “1” causes the Sequencer to suspend operation at the end of the internal
S/H's acquisition cycle and to wait until a rising edge appears at the SYNC pin. When a rising edge appears, the
S/H acquires the input signal magnitude and the ADC performs a conversion on the clock's next rising edge.
When the SYNC pin is used as an input, the Configuration register's “I/O Select” bit (Bit 7) must be set to a “0”.
With SYNC configured as an input, it is possible to synchronize the start of a conversion to an external event.
This is useful in applications such as digital signal processing (DSP) where the exact timing of conversions is
important.
When the LM12(H)454/8 are used in the “watchdog” mode with external synchronization, two rising edges on the
SYNC input are required to initiate two comparisons. The first rising edge initiates the comparison of the selected
analog input signal with Limit #1 (found in Instruction RAM “01”) and the second rising edge initiates the
comparison of the same analog input signal with Limit #2 (found in Instruction RAM “10”).
Bit 9 is the TIMER bit. When Bit 9 is set to “1”, the Sequencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no “watchdog” comparisons or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10 to “1” selects 8-bit + sign and when reset to “0”
selects 12-bit + sign.
Bit 11 is the “watchdog” comparison mode enable bit. When operating in the “watchdog” comparison mode, the
selected analog input signal is compared with the programmable values stored in Limit #1 and Limit #2 (see
Instruction RAM “01” and Instruction RAM “10”). Setting Bit 11 to “1” causes two comparisons of the selected
analog input signal with the two stored limits. When Bit 11 is reset to “0”, an 8-bit + sign or 12-bit + sign
(depending on the state of Bit 10 of Instruction RAM “00”) conversion of the input signal can take place.
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