Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
The LM12(H)454/8's “watchdog” mode is used to monitor a single-ended or differential signal's amplitude. Each
sampled signal has two limits. An interrupt can be generated if the input signal is above or below either of the
two limits. This allows interrupts to be generated when analog voltage inputs are “inside the window” or,
alternatively, “outside the window”. After a “watchdog” mode interrupt, the processor can then request a
conversion on the input signal and read the signal's magnitude.
The analog input multiplexer can be configured for any combination of single-ended or fully differential operation.
Each input is referenced to ground when a multiplexer channel operates in the single-ended mode. Fully
differential analog input channels are formed by pairing any two channels together.
The LM12454's multiplexer outputs and S/H inputs (MUXOUT+, MUXOUT− and S/H IN+, S/H IN−) provide the
option for additional analog signal processing. Fixed-gain amplifiers, programmable-gain amplifiers, filters, and
other processing circuits can operate on the signal applied to the selected multiplexer channel(s). If external
processing is not used, connect MUXOUT+ to S/H IN+ and MUXOUT− to S/H IN−.
The LM12(H)454/8's internal S/H is designed to operate at its minimum acquisition time (1.13 μs, 12 bits) when
the source impedance, R
S
, is ≤ 60Ω (f
CLK
≤ 8 MHz). When 60Ω < R
S
≤ 4.17 kΩ, the internal S/H's acquisition
time can be increased to a maximum of 4.88 μs (12 bits, f
CLK
= 8 MHz). See Section 2.1 (Instruction RAM “00”)
Bits 12–15 for more information.
An internal 2.5V bandgap reference output is available at pin 44. This voltage can be used as the ADC reference
for ratiometric conversion or as a virtual ground for front-end analog conditioning circuits. The V
REFOUT
pin should
be bypassed to ground with a 100 μF capacitor.
Microprocessor overhead is reduced through the use of the internal conversion FIFO. Thirty-two consecutive
conversions can be completed and stored in the FIFO without any microprocessor intervention. The
microprocessor can, at any time, interrogate the FIFO and retrieve its contents. It can also wait for the
LM12(H)454/8 to issue an interrupt when the FIFO is full or after any number (≤32) of conversions have been
stored.
Conversion sequencing, internal timer interval, multiplexer configuration, and many other operations are
programmed and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the LM12(H)458's operation. The diagnostic mode is
disabled in the LM12454. This mode internally connects the voltages present at the V
REFOUT
, V
REF+
, V
REF−
, and
GND pins to the internal V
IN+
and V
IN−
S/H inputs. This mode is activated by setting the Diagnostic bit (Bit 11) in
the Configuration register to a “1”. More information concerning this mode of operation can be found in Section
2.2.
Internal User-Programmable Registers
INSTRUCTION RAM
The instruction RAM holds up to eight sequentially executable instructions. Each 48-bit long instruction is divided
into three 16-bit sections. READ and WRITE operations can be issued to each 16-bit section using the
instruction's address and the 2-bit “RAM pointer” in the Configuration register. The eight instructions are located
at addresses 0000 through 0111 (A4–A1, BW = 0) when using a 16-bit wide data bus or at addresses 00000
through 01111 (A4–A0, BW = 1) when using an 8-bit wide data bus. They can be accessed and programmed in
random order.
Any Instruction RAM READ or WRITE can affect the sequencer's operation:
The Sequencer should be stopped by setting the RESET bit to a “1” or by resetting the START bit in the
Configuration Register and waiting for the current instruction to finish execution before any Instruction
RAM READ or WRITE is initiated. Bit 0 of the Configuration Register indicates the Sequencer Status. See
paragraph 2.2 for information on the Configuration Register.
A soft RESET should be issued by writing a “1” to the Configuration Register's RESET bit after any READ
or WRITE to the Instruction RAM.
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Product Folder Links: LM12454 LM12458 LM12H458