Datasheet

LM12454, LM12458, LM12H458
SNAS079A –MAY 2004–REVISED FEBRUARY 2006 www.ti.com
Pin Descriptions (continued)
Active high Direct Memory Access Request output. This output is designed to drive capacitive loads of 100 pF
or less. External buffers are necessary for driving higher load capacitances. It goes high whenever the number
DMARQ
of conversion results in the conversion FIFO equals a programmable value stored in the Interrupt Enable
register. It returns to a logic low when the FIFO is empty.
LM12(H)454/8 ground connection. It should be connected to a low resistance and inductance analog ground
GND
return that connects directly to the system power supply ground.
The eight (LM12(H)458) or four (LM12454) analog inputs. A given channel is selected through the instruction
IN0–IN7 (IN0–IN3
RAM. Any of the channels can be configured as an independent single-ended input. Any pair of channels,
LM12H454 LM12454)
whether adjacent or non-adjacent, can operate as a fully differential pair.
S/H IN+ S/H IN- The LM12454's non-inverting and inverting inputs to the internal S/H.
MUXOUT+ MUXOUT- The LM12454's non-inverting and inverting outputs from the internal multiplexer.
The negative reference input. The LM12(H)454/8 operate with 0V = V
REF-
= V
REF+
. This pin should be bypassed
V
REF-
to ground with a parallel combination of 10 µF and 0.1 µF (ceramic) capacitors.
The positive reference input. The LM12(H)454/8 operate with 0V = V
REF+
= V
A
+. This pin should be bypassed
V
REF+
to ground with a parallel combination of 10 µF and 0.1 µF (ceramic) capacitors.
V
REFOUT
The internal 2.5V bandgap's output pin. This pin should be bypassed to ground with a 100 µF capacitor.
FUNCTIONAL DESCRIPTION
The LM12454 and LM12(H)458 are multi-functional Data Acquisition Systems that include a fully differential 12-
bit-plus-sign self-calibrating analog-to-digital converter (ADC) with a two's-complement output format, an 8-
channel (LM12(H)458) or a 4-channel (LM12454) analog multiplexer, an internal 2.5V reference, a first-in-first-out
(FIFO) register that can store 32 conversion results, and an Instruction RAM that can store as many as eight
instructions to be sequentially executed. The LM12454 also has a differential multiplexer output and a differential
S/H input. All of this circuitry operates on only a single +5V power supply.
The LM12(H)454/8 have three modes of operation:
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode (“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration
capabilities. Charge re-distribution ADCs use a capacitor ladder in place of a resistor ladder to form an internal
DAC. The DAC is used by a successive approximation register to generate intermediate voltages between the
voltages applied to V
REF−
and V
REF+
. These intermediate voltages are compared against the sampled analog
input voltage as each bit is generated. The number of intermediate voltages and comparisons equals the ADC's
resolution. The correction of each bit's accuracy is accomplished by calibrating the capacitor ladder used in the
ADC.
Two different calibration modes are available; one compensates for offset voltage, or zero error, while the other
corrects both offset error and the ADC's linearity error.
When correcting offset only, the offset error is measured once and a correction coefficient is created. During the
full calibration, the offset error is measured eight times, averaged, and a correction coefficient is created. After
completion of either calibration mode, the offset correction coefficient is stored in an internal offset correction
register.
The LM12(H)454/8's overall linearity correction is achieved by correcting the internal DAC's capacitor mismatch.
Each capacitor is compared eight times against all remaining smaller value capacitors and any errors are
averaged. A correction coefficient is then created and stored in one of the thirteen internal linearity correction
registers. An internal state machine, using patterns stored in an internal 16 x 8-bit ROM, executes each
calibration algorithm.
Once calibrated, an internal arithmetic logic unit (ALU) uses the offset correction coefficient and the 13 linearity
correction coefficients to reduce the conversion's offset error and linearity error, in the background, during the 12-
bit + sign conversion. The 8-bit + sign conversion and comparison modes use only the offset coefficient. The 8-
bit + sign mode performs a conversion in less than half the time used by the 12-bit + sign conversion mode.
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