Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- KEY SPECIFICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- OPERATING RATINGS
- CONVERTER CHARACTERISTICS
- CONVERTER AC CHARACTERISTICS
- DC CHARACTERISTICS
- INTERNAL REFERENCE CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- DIGITAL TIMING CHARACTERISTICS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL DYNAMIC PERFORMANCE CHARACTERISTICS
- TEST CIRCUITS and WAVEFORMS
- TIMING DIAGRAMS
LM12454, LM12458, LM12H458
www.ti.com
SNAS079A –MAY 2004–REVISED FEBRUARY 2006
Figure 44. Interrupt and DMARQ
22: INT high from RD low
23: DMARQ low from RD low
Pin Descriptions
Analog and digital supply voltage pins. The LM12(H)454/8's supply voltage operating range is +3.0V to +5.5V.
Accuracy is ensured only if V
A
+ and V
D
+ are connected to the same power supply. Each pin should have a
V
A
+ V
D
+
parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors connected
between it and ground.
The internal data input/output TRI-STATE buffers are connected to these pins. These buffers are designed to
drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load capacitances.
These pins allows the user a means of instruction input and data output. With a logic high applied to the BW
D0–D15
pin, data lines D8–D15 are placed in a high impedance state and data lines D0–D7 are used for instruction
input and data output when the LM12(H)454/8 is connected to an 8-bit wide data bus. A logic low on the BW
pin allows the LM12(H)454/8 to exchange information over a 16-bit wide data bus.
Input for the active low READ bus control signal. The data input/output TRI-STATE buffers, as selected by the
RD logic signal applied to the BW pin, are enabled when RD and CS are both low. This allows the LM12(H)454/8
to transmit information onto the data bus.
Input for the active low WRITE bus control signal. The data input/output TRI-STATE buffers, as selected by the
WR logic signal applied to the BW pin, are enabled when WR and CS are both low. This allows the LM12(H)454/8
to receive information from the data bus.
Input for the active low Chip Select control signal. A logic low should be applied to this pin only during a READ
CS or WRITE access to the LM12(H)454/8. The internal clocking is halted and conversion stops while Chip Select
is low. Conversion resumes when the Chip Select input signal returns high.
Address Latch Enable input. It is used in systems containing a multiplexed data bus. When ALE is asserted
high, the LM12(H)454/8 accepts information on the data bus as a valid address. A high-to-low transition will
ALE latch the address data on A0–A4 while the CS is low. Any changes on A0–A4 and CS while ALE is low will not
affect the LM12(H)454/8. See Figure 42. When a non-multiplexed bus is used, ALE is continuously asserted
high. See Figure 43.
External clock input pin. The LM12(H)454/8 operates with an input clock frequency in the range of 0.05 MHz to
CLK
10.0 MHz.
The LM12(H)454/8's address lines. They are used to access all internal registers, Conversion FIFO, and
A0–A4
Instruction RAM.
Synchronization input/output. When used as an output, it is designed to drive capacitive loads of 100 pF or
less. External buffers are necessary for driving higher load capacitances. SYNC is an input if the Configuration
register's “I/O Select” bit is low. A rising edge on this pin causes the internal S/H to hold the input signal. The
next rising clock edge either starts a conversion or makes a comparison to a programmable limit depending on
SYNC
which function is requested by a programming instruction. This pin will be an output if “I/O Select” is set high.
The SYNC output goes high when a conversion or a comparison is started and low when completed. (See
Section 2.2). An internal reset after power is first applied to the LM12(H)454/8 automatically sets this pin as an
input.
Bus Width input pin. This input allows the LM12(H)454/8 to interface directly with either an 8- or 16-bit data
BW bus. A logic high sets the width to 8 bits and places D8–D15 in a high impedance state. A logic low sets the
width to 16 bits.
Active low interrupt output. This output is designed to drive capacitive loads of 100 pF or less. External buffers
are necessary for driving higher load capacitances. An interrupt signal is generated any time a non-masked
INT
interrupt condition takes place. There are eight different conditions that can cause an interrupt. Any interrupt is
reset by reading the Interrupt Status register. (See Section 2.3.)
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