Datasheet

LM12454, LM12458, LM12H458
SNAS079A –MAY 2004–REVISED FEBRUARY 2006 www.ti.com
12: WR high to next ALE high
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
Figure 43. Non-Multiplexed Data Bus (ALE = 1)
8: RD pulse width
9: RD high to next RD or WR low
11: WR pulse width
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
19: Address invalid from RD or WR high (hold time)
20: CS low or address valid to RD low
21: CS low or address valid to WR low
V
A
+ = V
D
+ = +5V, t
R
= t
F
= 3 ns, C
L
= 100 pF for the INT, DMARQ, D0–D15 outputs.
22 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated
Product Folder Links: LM12454 LM12458 LM12H458