Datasheet

LM12454, LM12458, LM12H458
www.ti.com SNAS079A –MAY 2004–REVISED FEBRUARY 2006
Figure 41. TRI-STATE Test Circuits and Waveforms
TIMING DIAGRAMS
V
A
+ = V
D
+ = +5V, t
R
= t
F
= 3 ns, C
L
= 100 pF for the INT, DMARQ, D0–D15 outputs.
Figure 42. Multiplexed Data Bus
1, 3: CS or Address valid to ALE low set-up time.
2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width
6: RD high to next ALE high
7: ALE low to RD low
8: RD pulse width
9: RD high to next RD or WR low
10: ALE low to WR low
11: WR pulse width
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