LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 LM12454/LM12458/LM12H458 12-Bit + Sign Data Acquisition System with Self-Calibration Check for Samples: LM12454, LM12458, LM12H458 FEATURES 1 • 23 Three operating modes: 12-bit + sign, 8-bit + sign, and “watchdog” Single-ended or differential inputs Built-in Sample-and-Hold and 2.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM * Pin names in ( ) apply to the obsolete LM12454 and LM12H454. Figure 1. See Package Number FN0044A Figure 2.
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LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 ABSOLUTE MAXIMUM RATINGS www.ti.com (1) (2) Supply Voltage (VA+ and VD+) 6.0V −0.3V to (V+ + 0.3V) Voltage at Input and Output Pins, except analog inputs − 5V to (V+ + 5V) Voltage at Analog Inputs |VA+ − VD+| 300 mV Input Current at Any Pin Package Input Current (3) ±5 mA (3) ±20 mA Power Dissipation, PQFP (4) (TA = 25°C) 875 mW −65°C to +150°C Storage Temperature Lead Temperature PQFP, Infrared, 15 sec.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 CONVERTER CHARACTERISTICS (1) (2) (3) (4) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise specified.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com CONVERTER CHARACTERISTICS (1) (2) (3) (4) (continued) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 CONVERTER AC CHARACTERISTICS (1) (2) (3) (4) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise specified.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com CONVERTER AC CHARACTERISTICS (1) (2) (3) (4) (continued) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 DC CHARACTERISTICS (1) (2) (3) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, fCLK = 8.0 MHz (LM12H454/8) or fCLK = 5.0 MHz (LM12458), and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com INTERNAL REFERENCE CHARACTERISTICS (1) (2) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol Parameter Conditions Typical Limits (4) Units 2.5 ±4% V (max) (3) VREFOUT Internal Reference Output Voltage 2.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 DIGITAL TIMING CHARACTERISTICS (1) (2) (3) The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, tr = tf = 3 ns, and CL = 100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com VREF = VREF+ − VREF− VIN = VIN+ − VIN− GND ≤ VIN+ ≤VA+ GND ≤ VIN− ≤VA+ VREF+ − VREF− = 4.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 VREF = VREF+ − VREF− VA+ = 5V Figure 4.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com Figure 5. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles Figure 6. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle Figure 7.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 TYPICAL PERFORMANCE CHARACTERISTICS (1) The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8bit + sign and “watchdog” modes is equal to or better than shown. (1) Linearity Error Change vs. Clock Frequency Linearity Error Change vs. Temperature Figure 8. Figure 9. Linearity Error Change vs. Reference Voltage Linearity Error Change vs.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) (1) The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8bit + sign and “watchdog” modes is equal to or better than shown. 16 Full-Scale Error Change vs. Reference Voltage Full-Scale Error vs. Supply Voltage Figure 14. Figure 15. Zero Error Change vs. Clock Frequency Zero Error Change vs.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (1) The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8bit + sign and “watchdog” modes is equal to or better than shown. Analog Supply Current vs. Temperature Digital Supply Current vs. Clock Frequency Figure 20. Figure 21. Digital Supply Current vs. Temperature VREFOUT Load Regulation Figure 22.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com TYPICAL DYNAMIC PERFORMANCE CHARACTERISTICS The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. 18 Bipolar Signal-to-Noise Ratio vs. Input Frequency Bipolar Signal-to-Noise + Distortion Ratio vs. Input Frequency Figure 25. Figure 26. Bipolar Signal-to-Noise + Distortion Ratio vs. Input Signal Level Bipolar Spectral Response with 1.028 kHz Sine Wave Input Figure 27.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 TYPICAL DYNAMIC PERFORMANCE CHARACTERISTICS (continued) The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. Bipolar Spectral Response with 40 kHz Sine Wave Input Bipolar Spurious Free Dynamic Range Figure 31. Figure 32. Unipolar Signal-to-Noise Ratio vs. Input Frequency Unipolar Signal-to-Noise + Distortion Ratio vs. Input Frequency Figure 33. Figure 34.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com TYPICAL DYNAMIC PERFORMANCE CHARACTERISTICS (continued) The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. Unipolar Spectral Response with 10 kHz Sine Wave Input Unipolar Spectral Response with 20 kHz Sine Wave Input Figure 37. Figure 38. Unipolar Spectral Response with 40 kHz Sine Wave Input Figure 39. TEST CIRCUITS and WAVEFORMS Figure 40.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Figure 41. TRI-STATE Test Circuits and Waveforms TIMING DIAGRAMS VA+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15 outputs. Figure 42. Multiplexed Data Bus 1, 3: CS or Address valid to ALE low set-up time. 2, 4: CS or Address valid to ALE low hold time.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com 12: WR high to next ALE high 13: WR high to next WR or RD low 14: Data valid to WR high set-up time 15: Data valid to WR high hold time 16: RD low to data bus out of TRI-STATE 17: RD high to TRI-STATE 18: RD low to data valid (access time) Figure 43.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Figure 44. Interrupt and DMARQ 22: INT high from RD low 23: DMARQ low from RD low Pin Descriptions VA+ VD+ Analog and digital supply voltage pins. The LM12(H)454/8's supply voltage operating range is +3.0V to +5.5V. Accuracy is ensured only if VA+ and VD+ are connected to the same power supply. Each pin should have a parallel combination of 10 µF (electrolytic or tantalum) and 0.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com Pin Descriptions (continued) DMARQ Active high Direct Memory Access Request output. This output is designed to drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. It goes high whenever the number of conversion results in the conversion FIFO equals a programmable value stored in the Interrupt Enable register. It returns to a logic low when the FIFO is empty.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 The LM12(H)454/8's “watchdog” mode is used to monitor a single-ended or differential signal's amplitude. Each sampled signal has two limits. An interrupt can be generated if the input signal is above or below either of the two limits. This allows interrupts to be generated when analog voltage inputs are “inside the window” or, alternatively, “outside the window”.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com The three sections in the Instruction RAM are selected by the Configuration Register's 2-bit “RAM Pointer”, bits D8 and D9. The first 16-bit Instruction RAM section is selected with the RAM Pointer equal to “00”. This section provides multiplexer channel selection, as well as resolution, acquisition time, etc.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Table 1.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com Table 2.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Bits 12–15 are used to store the user-programmable acquisition time. The Sequencer keeps the internal S/H in the acquisition mode for a fixed number of clock cycles (nine clock cycles, for 12-bit + sign conversions and two clock cycles for 8-bit + sign conversions or “watchdog” comparisons) plus a variable number of clock cycles equal to twice the value stored in Bits 12–15.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com Bit 1 is the LM12(H)454/8's system RESET bit. Writing a “1” to Bit 1 stops the Sequencer (resetting the Configuration register's START/STOP bit), resets the Instruction pointer to “000” (found in the Interrupt Status register), clears the Conversion FIFO, and resets all interrupt flags.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Bit 11 is the Diagnostic bit and is available only in the LM12(H)458. It can be activated by setting it to a “1” (the Test bit must be reset to a “0”). The Diagnostic mode, along with a correctly chosen instruction, allows verification that the LM12(H)458's ADC is performing correctly. When activated, the inverting and non-inverting inputs are connected as shown in Table 3.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com The completion of a full auto-zero and linearity self-calibration generates Interrupt 4. Interrupt 5 is generated when the Sequencer encounters an instruction that has its Pause bit (Bit 1 in Instruction RAM “00”) set to “1”. The LM12(H)454/8 issues Interrupt 6 whenever it senses that its power supply voltage is dropping below 4V (typ). This interrupt indicates the potential corruption of data returned by the LM12(H)454/8.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Bit 0 is set to “1” when a “watchdog” comparison limit interrupt has taken place. Bit 1 is set to “1” when the Sequencer has reached the address stored in Bits 8–10 of the Interrupt Enable register. Bit 2 is set to “1” when the Conversion FIFO's limit, stored in Bits 11–15 of the Interrupt Enable register, has been reached. Bit 3 is set to “1” when the single-sample auto-zero has been completed.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com DMA operation is optimized through the use of the 16-bit data bus connection (a logic “0” applied to the BW pin). Using this bus width allows DMA controllers that have single address Read/Write capability to easily unload the FIFO. Using DMA on an 8-bit data bus is more difficult. Two read operations (low byte, high byte) are needed to retrieve each conversion result from the FIFO.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a “1”, state 2 is 76 clock cycles long. If the Configuration register's bit 3 is set to a “1”, state 2 is 4944 clock cycles long. State 3: Run the internal 16-bit Timer. The number of clock cycles for this state varies according to the value stored in the Timer register.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com Figure 45.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 DESIGN CONSIDERATIONS REFERENCE VOLTAGE The difference in the voltages applied to the VREF+ and VREF− defines the analog input voltage span (the difference between the voltages applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist.
LM12454, LM12458, LM12H458 SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 www.ti.com NOISE The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects of the noise sources. POWER SUPPLIES Noise spikes on the VA+ and VD+ supply lines can cause conversion errors; the comparator will respond to the noise.
LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Improper termination of digital lines. Improper termination can result in energy reflections that build up to cause overshoot that goes above the supply potential and undershoot that goes below ground. It is never good to drive a device beyond the supply rails, unless the device is specifically designed to handle this situation, but the LM12(H)458 is more sensitive to this condition that most devices.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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