Datasheet

EN
COMPARATOR
SPI
UVLO
SEQUENCER
REGISTERS
LDO
GND
GND
LDO
CLK
VIN_IO
DO
DI
CS
SW1
BUCK1
EN
FB_B1
GND_B1
SW_B1
VIN_B1
EN
SW3
BUCK3
GND_B3
FB_B3
SW_B3
VIN_B3
T
SD
EN
VCOMP
IRQ
RESET
STANDBY
HL_B3
GND
VIN
CONTROL
LOGIC
OVLO
EN
SW2
BUCK2
GND_B2
FB_B2
SW_B2
VIN_B2
HL_B2
LM10506
www.ti.com SNVS729E –SEPTEMBER 2011–REVISED MARCH 2013
GENERAL DESCRIPTION
LM10506 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and
processors. It operates cooperatively and communicates with processors over an SPI interface with output
Voltage programmability and Standby Mode.
The device incorporates three high-efficiency synchronous buck regulators and one LDO that deliver four output
voltages from a single power source. The device also includes a SPI-programmable Comparator Block that
provides an interrupt output signal.
Figure 21. Internal Block Diagram of the LM10506 PMIC
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