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LM10506

www.ti.com

SNVS729E –SEPTEMBER 2011–REVISED MARCH 2013

LM10506 Triple Buck + LDO Power Management Unit

Check for Samples: LM10506

FEATURES

DESCRIPTION

The LM10506 is an advanced PMU containing three

• Three Highly Efficient Programmable Buck

configurable, high-efficiency buck regulators for

Regulators

supplying variable voltages. The device is ideal for

– Integrated FETs with Low R

DSON

supporting ASIC and SOC designs for Solid-State

– Bucks Operate With Their Phases Shifted

and Flash drives.

to Reduce the Input Current Ripple and

The LM10506 operates cooperatively with ASIC to

Capacitor Size

optimize the supply voltage for low-power conditions

– Programmable Output Voltage via the SPI

and Power Saving modes via the SPI interface. It

Interface also supports a 100 mA LDO and a programmable

Interrupt Comparator.

– Overvoltage and Undervoltage Lockout

– Automatic Internal Soft Start With Power-

On Reset

– Current Overload and Thermal Shutdown

Protection

– Bypass Mode Available on Bucks 1 and 2

– PFM Mode for Low-Load, High-Efficiency

Operation

• Low-Dropout LDO 3.2V, 100 mA

• SPI-Programmable Interrupt Comparator (2.0V

to 4.0V)

• Alternate Buck V

OUTS

Selectable via H/L Logic

Pins

• RESET, STANDBY Pins

APPLICATIONS

• Solid-State Drives

KEY SPECIFICATIONS

• Programmable Buck Regulators:

– Buck 1: 1.1V to 3.6V; 1.3A

– Buck 2: 1.1V to 3.6V; 400 mA

– Buck 3: 0.7V to 1.335V; 600 mA

• ±3% feedback voltage accuracy

• Up to 95% efficient buck regulators

• 2MHz switching frequency for smaller inductor

size

• 2.8 x 2.8 mm, 0.4 mm pitch, 34-bump DSBGA

package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 LM10506 Triple Buck + LDO Power Management Unit Check for Samples: LM10506 FEATURES DESCRIPTION • The LM10506 is an advanced PMU containing three configurable, high-efficiency buck regulators for supplying variable voltages. The device is ideal for supporting ASIC and SOC designs for Solid-State and Flash drives.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com Figure 1. Typical Application Diagram IO input ` supply C9 2.2 F Reset VIN_IO LM10506 STANDBY CS SPI DI System DO Control VIN C8 2.2 F Power Supply 3.3/5.0V CONTROL LOGIC and REGISTERS CLK VIN_B1 C5 4.7 F VIN_B2 C6 4.7 F VCOMP COMP LDO IRQ LDO SW_B1 BUCK1 C4 4.7 F L1 2.2 H FB_B1 BUCK2 2.2 H 1.1V to 3.6V L3 VIN_B3 H/L B3 H/L B2 GND GND BUCK3 GND Host 2 Domain VCCQ 400 mA C2 22 F FB_B2 SW_B3 C7 4.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Table 2. Output Voltage Configurations for LM10506-A, LM10506-D, LM10506-B (1) Regulator VOUT if H/L=High (B2, B3) VOUT if H/L=Low (B2, B3) VOUT if STANDBY=High (STANDBY Mode) VOUT Maximum Output Current Typical Application Comments Buck 1 (1) 3.0V 3.0V Off 1.1V to 3.6V; 50 mV steps 1.3A VCC Flash Buck 2 (1) 2.0V 1.8V Off 1.1V to 3.6V; 50 mV steps 400 mA VCCQ Interface Buck 3 (1) 1.2V 1.0V VNOM - 7% 0.7V to 1.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com LM10506 Pin Descriptions I/O (1) Type (1) VIN_B1 I P Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) VIN, VCOMP −0.3V to +6.0V (6.25V on -B only) VIN_IO, VIN_B1, VIN_B2, VIN_B3, SPI_CS, SPI_DI, SPI_CLK, SPI_DO, IRQ, HL_B2, HL_B3, STANDBY, RESET, SW_B1, SW_B2, SW_B3, FB_B1, FB_B2, FB_B3, LDO −0.3V to +6.0V (6.25V on -B only) Junction Temperature (TJ-MAX) 150°C −65°C to 150°C Storage Temperature ESD Rating (1) (2) (3) Human Body Model (HBM) 2.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com General Electrical Characteristics(1)(2) (continued) Unless otherwise noted, VIN = 5.0V where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Buck 2 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VIN = 5.0V where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com Buck 3 Electrical Characteristics(1)(2)(3) (continued) Unless otherwise noted, VIN = 5.0V where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Typical Performance Characteristics Efficiency of Buck 2: VIN=5.0V, VOUT=1.8V and 3.0V 100 90 90 80 80 EFFICIENCY (%) EFFICIENCY (%) Efficiency of Buck 1: VIN=5.0V, VOUT=3.0V 100 70 60 50 70 60 50 40 40 30 30 20 VOUT = 1.8V VOUT = 3.0V 20 1 10 100 IOUT(mA) 1k 10k 1 10 100 IOUT(mA) Figure 2. Figure 3. Startup of Buck 1: VIN=3.3V (VOUT=3.0V, IOUT=1.0A) Startup of Buck 1: VIN=5.0V (VOUT=3.0V, IOUT=1.0A) 200 µs/ 1 1.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Buck 2 VOUT vs. IOUT VIN=5.0V, VOUT=1.8V 3000 1810 2998 1808 2996 1806 2994 1804 VOUT(mV) VOUT(mV) Buck 1 VOUT vs. IOUT VIN=5.0V, VOUT=3.0V 2992 2990 2988 1800 1798 2986 1796 2984 1794 2982 1792 2980 100 1790 300 500 700 900 1100 1300 IOUT(mA) 100 200 250 300 IOUT(mA) Figure 9. Buck 2 VOUT vs. IOUT VIN=5.0V, VOUT=3.0V Buck 3 VOUT vs. IOUT VIN=5.0V, VOUT=1.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Buck 2 VOUT vs. VIN VOUT=3.0V, IOUT=400mA Buck 3 VOUT vs VIN VOUT=1.0V, IOUT=600mA 2.995 1.010 2.990 1.005 VOUT(V) 1.015 VOUT(V) 3.000 2.985 1.000 2.980 0.995 2.975 0.990 2.970 0.985 3.5 4.0 4.5 5.0 VIN(V) 3.0 4.0 VIN(V) Figure 14. Figure 15. Buck 3 VOUT vs VIN VOUT=1.2V, IOUT=600mA 3.5 4.5 5.0 LDO Startup Time from VIN Rise 1 1.00V/ 2 1.00V/ 1.215 5.00 ms/ 1.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) From Buck 2 Startup to Buck 3 Startup 1 1.00V/ 2 1.00V/ 1 BUCK2 2 BUCK3 1.00 ms/ Figure 20.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 GENERAL DESCRIPTION LM10506 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and processors. It operates cooperatively and communicates with processors over an SPI interface with output Voltage programmability and Standby Mode.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com SPI DATA INTERFACE The device is programmable via 4-wire SPI Interface. The signals associated with this interface are CS, DI, DO and CLK. Through this interface, the user can enable/disable the device, program the output voltages of the individual Bucks and of course read the status of Flag registers.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Registers Configurable Via The SPI Interface Addr 0x00 0x07 0x08 0x09 0x0A Reg Name Buck 3 Voltage Buck 1 Voltage Buck 2 Voltage Standby Mode Voltage for Buck 3 Buck Control Bit R/W Default Description Notes 7 — 6 R/W Buck 3 Voltage Code[6] HL_B3=1 → 0x64 (1.2V) 5 R/W Buck 3 Voltage Code[5] HL_B3=0 → 0x3C (1.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Addr 0x0B 0x0C 0x0D 0x0E Reg Name Comparator Control Interrupt Enable Interrupt Status MISC Control www.ti.com Bit R/W Default 7 R/W 0 Comp_hyst[0] Description Doubles Comparator hysteresis Notes 6 R/W 0 Comp_thres[5] Programmable range of 2.0V to 4.0V, step size = 31.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Voltage code Voltage Voltage code Voltage 0x0C 1.70 0x2C 3.30 0x0D 1.75 0x2D 3.35 0x0E 1.80 0x2E 3.40 0x0F 1.85 0x2F 3.45 0x10 1.90 0x30 3.50 0x11 1.95 0x31 3.55 0x12 2.00 0x32 3.60 0x13 2.05 0x33 3.60 0x14 2.10 0x34 3.60 0x15 2.15 0x35 3.60 0x16 2.20 0x36 3.60 0x17 2.25 0x37 3.60 0x18 2.30 0x38 3.60 0x19 2.35 0x39 3.60 0x1A 2.40 0x3A 3.60 0x1B 2.45 0x3B 3.60 0x1C 2.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage 0x19 0.825 0x39 0.985 0x59 1.145 0x79 1.305 0x1A 0.830 0x3A 0.990 0x5A 1.150 0x7A 1.310 0x1B 0.835 0x3B 0.995 0x5B 1.155 0x7B 1.315 0x1C 0.840 0x3C 1.000 0x5C 1.160 0x7C 1.320 0x1D 0.845 0x3D 1.005 0x5D 1.165 0x7D 1.325 0x1E 0.850 0x3E 1.010 0x5E 1.170 0x7E 1.330 0x1F 0.855 0x3F 1.015 0x5F 1.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 BUCK REGULATORS OPERATION A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground and a feedback path. The following figure shows the block diagram of each of the three buck regulators integrated in the device. CONTROL G CIN P D D N S L SW COUT PGND VOUT G FB S VIN PVIN U1 LM10506 GND Figure 24.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com In Forced PWM Mode the bucks always operate in PWM mode regardless of the output current. In Automatic Mode, if the output current is less than 70 mA (typ.), the bucks automatically transition into PFM (Pulse Frequency Modulation) operation to reduce the current consumption. At higher than 100 mA (typ.) they operate in PWM mode. This increases the efficiency at lower output currents. The 30 mA (typ.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 25), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com Equivalent Circuit of Bypass Operation of Buck 1 High Side FET VIN_B1 DCR 100 m Max. Ideal Inductor, no resistance VOUT Buck1 SW_B1 Model of Inductor Load Capacitance Load Resistance FB_B1 Bypass FET Equivalent Circuit of Bypass Operation of Buck 2 (Not Applicable to LM10506-B) High Side FET VIN_B2 DCR 100 m Max.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Device Operating Modes STARTUP SEQUENCE The startup mode of the LM10506 will depend on the input voltage. Once VIN reaches the UVLO threshold, there is a 15 msec delay before the LM10506 determines how to set up the buck regulators. If VIN is below 3.6V, then Buck 1 and Buck 2 will be in bypass mode, see Bypass-FET Operation on Buck 1 and Buck 2 (Applies to Buck 1 only on LM10506-B) for functionality description.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com 5.7V 5.6V 3.5V 3.5V 2.9V 2.6V ~2.25V VIN BG/BIAS UVLO 15 ms 15 ms LDO 3.2V 3.5V 3.5V 2 ms 2 ms 2 ms 1.1V Buck1 2.6V 2 ms 2 ms 2 ms 2 ms Buck 2 (Except LM10506-B) 2 ms 1.1V Buck2 LM10506 -B Only. 2 ms 2 ms 2 ms 1.1V PSML 2 ms 2.6V 2 ms Buck3 Comparator OVLO B1 en Bypass B2 en Bypass BYPASS OPERATION Standby UVLO STARTUP BYPASS OPERATION OVLO STARTUP STANDBY UVLO Figure 26.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 STANDBY Pin When the STANDBY pin is asserted high, the LM10506 will enter Standby Mode. While in Standby Mode, Buck 1 and Buck 2 are disabled. Buck 3’s output voltage is transitioned to the PSML (Programmable Standby Mode Level) as set by register 0x09. The STANDBY pin is internally pulled down, and there is a 1 second delay during powerup before the state of the STANDBY pin is checked.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com HL_B2, HL_B3 FUNCTION The HL_B2/3 pins are digital pins which control alternate voltage selections of Buck 2 and Buck 3, respectively. HL_B2 has an internal pulldown which defaults to a 1.8V output voltage selection for Buck 2. Alternatively, if HL_B2 is driven high, an output voltage of 3.0V (or 2.0V for LM10506-A) is selected. HL_B3 has an internal pullup which defaults to a 1.2V output voltage selection for Buck 3.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 COMPARATOR The comparator on the LM10506 takes its inputs from the VCOMP pin and an internal threshold level which is programmed by the user. The threshold level is programmable between 2.0 and 4.0V with a step of 31 mV and a default comp code of 0x19. The output of the comparator is the IRQ pin. Its polarity can be changed using Register 0x0E bit 0.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com External Components Selection All three switchers require an input capacitor and an output inductor-capacitor filter. These components are critical to the performance of the device. All three switchers are internally compensated and do not require external components to achieve stable operation. The output voltages of the bucks can be programmed through the SPI pins.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 • • • • • • • IRIPPLE: Peak-to-Peak inductor current VOUT: Output voltage VIN: Input voltage L: Inductor value in Henries at IOUTMAX F: Switching frequency, Hertz D: Estimated duty factor EFF: Estimated power supply efficiency (2) ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst-case conditions, etc.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 The device is designed to be used with ceramic capacitors on the outputs of the buck regulators. The recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over voltage and temperature. The recommended value for the output capacitors is 22 μF, 6.3V with an ESR of 2mΩ or less. The output capacitors need to be mounted as close as possible to the output/ground pins of the device.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS current rating. Capacitor RMS current estimated as follows: © • I2RIPPLE 12 § © IRMSCIN = D x §I2OUT + IRMSCIN: estimated input capacitor RMS current. (9) PCB Layout Considerations PC board layout is an important part of DC-DC converter design.
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LM10506 www.ti.com SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 Figure 29. Possible PCB Layout Configuration to Use 6X Through Hole Vias in the Middle Outside 7x7 array 0.4 mm DSBGA 34-bump, with 24 peripheral and 6 inner vias = 30 individual signals PCB LAYOUT THERMAL DISSIPATION FOR DSBGA PACKAGE 1. Position ground layer as close as possible to DSBGA package. Second PCB layer is usually good option. LM10506 evaluation board is a good example. 2. Draw power traces as wide as possible.
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LM10506 SNVS729E – SEPTEMBER 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 34 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM10506TME-A/NOPB DSBGA YFR 34 250 178.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.02 3.02 0.76 4.0 8.0 Q1 LM10506TME/NOPB DSBGA YFR 34 250 178.0 8.4 3.02 3.02 0.76 4.0 8.0 Q1 LM10506TMX-A/NOPB DSBGA YFR 34 3000 178.0 8.4 3.02 3.02 0.76 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10506TME-A/NOPB DSBGA YFR 34 250 210.0 185.0 35.0 LM10506TME/NOPB DSBGA YFR 34 250 210.0 185.0 35.0 LM10506TMX-A/NOPB DSBGA YFR 34 3000 210.0 185.0 35.0 LM10506TMX/NOPB DSBGA YFR 34 3000 210.0 185.0 35.
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MECHANICAL DATA YFR0034xxx D 0.600±0.075 E TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE TME34XXX (Rev B) D: Max = 2.84 mm, Min = 2.78 mm E: Max = 2.84 mm, Min = 2.78 mm 4215092/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.