Datasheet

SCLK
SDI
tt
CSH
t tt
CSS
t
16
th
Clock
SCLK
tt
CSH
t tt
CSS
t
D7 D1 D0
1
st
Clock 8
th
Clock
tt
H
t
t
OD
t
OZD
SCLK
SDI
tt
PL
t
Valid Data Valid Data
tt
PH
t
tt
SU
t tt
H
t
16
th
Clock
LDC1000
www.ti.com SNOSCX2 –SEPTEMBER 2013
TIMING DIAGRAMS
Unless otherwise noted, all limits specified at TA = 25°C, VDD=5.0, VIO=3.3, 10pF capacitive load in parallel with
a 10kΩ load on SDO. Specified by design; not production tested.
Figure 5. Write Timing Diagram
Table 2.
PARAMETER CONDITIONS MIN TYP MAX UNIT
F
SCLK
Serial Clock Frequency 4 MHz
t
PH
SCLK Pulse Width High F
SCLK
=4Mhz 0.4/Fsclk s
t
PL
SCLK Pulse Width Low F
SCLK
=4Mhz 0.4/Fsclk s
t
SU
SDI Setup Time 10 ns
t
H
SDI Hold Time 10 ns
Figure 6. Read Timing Diagram
PARAMETER CONDITIONS MIN TYP MAX UNIT
t
ODZ
SDO Driven-to-Tristate Measured at 10% / 90% point 20 ns
Time
t
OZD
SDO Tristate-to-Driven Measured at 10% / 90% point 20 ns
Time
t
OD
SDO Output Delay Time 20 ns
t
CSS
CSB Setup Time 20 ns
t
CSH
CSB Hold Time 20 ns
t
IAG
Inter-Access Gap 100 ns
t
DRDYB
Data ready pulse width Data ready pulse at every 1/ODR if 1/f
sensor
s
no data is read
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