Datasheet

CSB
SDI
SCLK
Read DATA
1
tDATA FIELDt
SDO
R/Wb A6 A5 A4 A3 A2 A1 A0 Write DATA
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tCOMMAND FIELDt
High-Z
tSingle Access Cyclet
Data (8-bits)
C6C7 C5 C4 C3 C2 C1 C0 D7
(MSB)
D6 D5 D4 D3 D2 D1 D0
(LSB)
D7
(MSB)
D6 D5 D4 D3 D2 D1 D0
(LSB)
Address (7-bits)
R/Wb = Read/Write
0: Write Data
1: Read Data
LDC1000
www.ti.com SNOSCX2 –SEPTEMBER 2013
Table 21. Frequency Counter LSB
Address = 0x23, Default=NA, Direction=RO
Bit Field Field Name Description
7:0 ODR LSB (ODR[7:0]) LSB of Output data rate. Sensor frequency can be calculated using the
output data rate. Please refer to the Measuring Inductance.
Table 22. Frequency Counter Mid-Byte
Address = 0x24, Default=NA, Direction=RO
Bit Field Field Name Description
7:0 ODR Mid byte (ODR[15:8]) Middle Byte of Output data rate
Table 23. Frequency Counter MSB
Address = 0x25, Default=NA, Direction=RO
Bit Field Field Name Description
7:0 ODR MSB (ODR[23:16]) MSB of Output data rate
Care must be taken to ensure that Proximity Data[15:0] and Frequency Counter[23:0] are all from same
conversion. Conversion data is updated to these registers only when a read is initiated on 0x21 register. If the
read is delayed between subsequent conversions, these registers are not updated until another read is initiated
on 0x21.
DIGITAL INTERFACE
The LDC1000 utilizes a 4-wire SPI interface to access control and data registers. The LDC1000 is an SPI slave
device and does not initiate any transactions.
SPI Description
A typical serial interface transaction begins with an 8-bit instruction, which is comprised of a read/write bit (MSB,
R=1) and a 7 bit address of the register, followed by a Data field which is typically 8 bits. However, the data field
can be extended to a multiple of 8 bits by providing sufficient SPI clocks. Refer to the Extended SPI Transactions
section below.
Figure 17. Serial Interface Protocol
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