Datasheet

TCM BUS
TCM BUS
72 Bit data + ECC
72 Bit data + ECC
Upper 32 bits data &
4 ECC bits
Lower 32 bits data &
4 ECC bits
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
Upper 32 bits data &
4 ECC bits
Lower 32 bits data &
4 ECC bits
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
TCRAM
Interface 1
Cortex-R4F
B0
TCM
B1
TCM
TCRAM
Interface 2
TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
6.11 Tightly Coupled RAM Interface Module
Figure 6-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.
Figure 6-10. TCRAM Block Diagram
6.11.1 Features
The features of the Tightly Coupled RAM (TCRAM) Module are:
• Acts as slave to the BTCM interface of the Cortex-R4F CPU
• Supports the internal ECC scheme of the CPU by providing 64-bit data and 8-bit ECC code
• Monitors CPU Event Bus and generates single or multibit error interrupts
• Stores addresses for single and multibit errors
• Supports RAM trace module
• Provides CPU address bus integrity checking by supporting parity checking on the address bus
• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
• Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
• Supports auto-initialization of the RAM banks along with the ECC bits
6.11.2 TCRAM ECC Support
The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM.
It also stores the contents of the CPU ECC port in the ECC RAM when the CPU does a write to the RAM.
The TCRAM interface monitors the CPU event bus and provides registers for indicating single/multibit
errors and also for identifying the address that caused the single or multibit error. The event signaling and
the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515).
6.12 Parity Protection for Accesses to Peripheral RAMs
Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.
The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
78 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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