Datasheet

TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
Table 6-21. Master / Slave Access Matrix
MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Non-CPU CRC EMIF Slave Peripheral
Bus2 Interface: Accesses to Interface Control
OTP, ECC, Bank Program Flash Registers, All
7 and CPU Data Peripheral
RAM Memories, And
All System
Module Control
Registers And
Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
POM User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes
6.9.5 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
6.9.6 Parameter Overlay Module (POM) Considerations
• The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of
the memory overlay are configurable through the POM control registers. Care must be taken to ensure that the
overlay is mapped on to available memory.
• ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC errors will be
generated.
• POM overlay must not be enabled when the flash and internal RAM memories are swapped through the MEM
SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
• When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when
another master accesses the TCM flash. This results in a system hang.
– The POM implements a timeout feature to detect this exact scenario. The timeout needs to be enabled
whenever POM overlay is enabled.
– The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control
register (POMGLBCTRL, address = 0xFFA04000).
– In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO) flag is set in
the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can
be a prefetch abort for an instruction fetch or a data abort for a data fetch.
– The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If so, then
the application can assume that the timeout is caused by a bus contention between the POM transaction and
another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any
further aborts are not misinterpreted as having been caused due to a timeout from the POM.
74 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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