Datasheet

TMS570LS1224
www.ti.com SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015
Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END
FRAME
Reads return zeros, writes have no
PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B
effect
System Module -
Reads return zeros, writes have no
Frame 2 (see PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B
effect
SPNU515)
Reads return zeros, writes have no
PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B
effect
Generates address error interrupt, if
STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B
enabled
IOMM
Reads return zeros, writes have no
Multiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B
effect
Control Module
Reads return zeros, writes have no
DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B
effect
Reads return zeros, writes have no
DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB
effect
Reads return zeros, writes have no
DCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B
effect
Reads return zeros, writes have no
ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B
effect
Reads return zeros, writes have no
CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B
effect
Reads return zeros, writes have no
RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B
effect
Reads return zeros, writes have no
RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B
effect
Reads return zeros, writes have no
RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B
effect
Reads return zeros, writes have no
VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B
effect
Reads return zeros, writes have no
VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B
effect
System Module -
Reads return zeros, writes have no
Frame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B
effect
SPNU515)
6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an
imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to
handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s
program status register (CPSR).
6.9.4 Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
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