Datasheet

GCLK, GCLK2 (to CPU)
GCM
HCLK (to SYSTEM)
VCLK_peri (VCLK to peripherals on PCR1)
OSCIN
Low Power
Oscillator
10MHz
80kHz
1
0
4
5
/1..64
X1..256
/1..8
/1..32
6
*
VCLK
/1,2,..1024
Phase_seg2
CAN Baud Rate
Phase_seg1
VCLKA1
/1,2,..256
SPIx,MibSPIx
/2,3..2
24
LIN, SCI
SPI
LIN / SCI
/1,2..32
MibADCx
ADCLK
/1,2..65536
External Clock
ECLK
VCLK2
N2HETx
HRP
/1..64
LRP
/2
0
..2
5
Loop
Resolution Clock
High
Baud Rate
Baud Rate
N2HETx
TU
VCLK2
/1..64 X1..256 /1..8
/1..32 *
EXTCLKIN1
EXTCLKIN2
3
7
0
VCLK3 (to EMIF)
VCLK_sys (VCLK to system modules)
* the frequency at this node must not
exceed the maximum HCLK specifiation.
/1,2..256
I2C
I2C baud
rate
NTU[1]
NTU[0]
NTU[2]
NTU[3]
RTI
Reserved
Reserved
PLL#2 output
EXTCLKIN1
Prop_seg
DCANx
VCLK2 (to N2HETx and HTUx)
VCLKA1 (to DCANx)
0
1
4
5
6
VCLK
3
7
RTICLK (to RTI, DWWD)
/1, 2, 4, or 8
VCLK
1
4
5
6
3
7
/1..16
/1..16
/1..16
PLL #1 (FMzPLL)
PLL #2 (FMzPLL)
VCLK4 (to ePWM, eQEP, eCAP)
/1..16
TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
6.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in the figures below.
Figure 6-7. Device Clock Domains
64 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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