Datasheet

TMS570LS1224
www.ti.com SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015
Table 6-13. Clock Domain Descriptions (continued)
Clock Domain Name Default Clock Clock Source Description
Source Selection Register
VCLKA1 VCLK VCLKASRC
• Defaults to VCLK as the source
• Is disabled through the CDDISx registers bit 4
VCLKA2 VCLK VCLKASRC
• Defaults to VCLK as the source
• Is disabled through the CDDISx registers bit 5
VCLKA4_S VCLK VCLKACON1
• Defaults to VCLK as the source
• Frequency can be as fast as HCLK frequency
• Is disabled through the CDDISx registers bit 11
VCLKA4_DIVR VCLK VCLKACON1
• Divided down from the VCLKA4_S using the VCLKA4R field of
the VCLKACON1 register at address 0xFFFFE140
• Frequency can be VCLKA4_S/1, VCLKA4_S/2, ..., or
VCLKA4_S/8
• Default frequency is VCLKA4_S/2
• Is disabled separately through the VCLKACON1 register
VCLKA4_DIV_CDDIS bit only if the VCLKA4_S clock is not
disabled
RTICLK VCLK RCLKSRC
• Defaults to VCLK as the source
• If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
– Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
• Is disabled through the CDDISx registers bit 6
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