Datasheet

TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
5.7 Power Consumption Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
HCLK
= 160MHz 170
(1)
350
(2)
V
CC
digital supply current (operating mode)
mA
f
VCLK
= f
HCLK
/2; Flash in pipelined mode; V
CCmax
f
HCLK
= 180MHz 190
(1)
370
(2)
I
CC
LBIST/PBIST clock
215
(1)
470
(3)(4)
mA
frequency = 80MHz
V
CC
Digital supply current (LBIST/PBIST mode)
LBIST/PBIST clock
470
(3)(4)
mA
240
(1)
frequency = 90MHz
I
CCPLL
V
CCPLL
digital supply current (operating mode) V
CCPLL
= V
CCPLLmax
10 mA
I
CCIO
V
CCIO
Digital supply current (operating mode. No DC load, V
CCmax
10 mA
Single ADC
operational, 15
V
CCADmax
I
CCAD
V
CCAD
supply current (operating mode) mA
Both ADCs
operational, 30
V
CCADmax
Single ADC
operational, 3
AD
REFHImax
I
ADREFHI
AD
REFHI
supply current (operating mode) mA
Both ADCs
operational, 6
AD
REFHImax
read from 1 bank
and program
I
CCP
V
CCP
supply current 55 mA
another bank,
V
CCPmax
(1) The typical value is the average current for the nominal process corner and junction temperature of 25C.
(2) The maximum I
CC,
value can be derated
• linearly with voltage
• by 1 ma/MHz for lower operating frequency when f
HCLK
= 2 * f
VCLK
• for lower junction temperature by the equation below where T
JK
is the junction temperature in Kelvin and the result is in milliamperes.
170 - 0.068 e
0.0185 T
JK
(3) The maximum I
CC,
value can be derated
• linearly with voltage
• by 1.5 ma/MHz for lower operating frequency
• for lower junction temperature by the equation below where T
JK
is the junction temperature in Kelvin and the result is in milliamperes.
170 - 0.068 e
0.0185 T
JK
(4) LBIST and PBIST currents are for a short duration, typically less than 10ms. They are usually ignored for thermal calculations for the
device and the voltage regulator
44 Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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