Datasheet
Address Wait States
Data Wait States
RAM
Address Wait States
Data Wait States
Flash (Main Memory)
0MHz
0MHz
0MHz
0MHz
50MHz
0 1 3
0
0
0
150MHz
2
150MHz
1
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
Data Wait States
0MHz
0 1 3
150MHz
2
f
HCLK(max)
Flash (Data Memory)
100MHz
50MHz 100MHz
TMS570LS1224
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SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015
5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
Table 5-1. Clock Domain Timing Specifications
PARAMETER DESCRIPTION CONDITIONS MAX UNIT
Pipeline mode
160 MHz
enabled
PGE
Pipeline mode
50 MHz
disabled
f
HCLK
HCLK - System clock frequency
Pipeline mode
180 MHz
enabled
ZWT
Pipeline mode
50 MHz
disabled
f
GCLK
GCLK - CPU clock frequency f
HCLK
MHz
f
VCLK
VCLK - Primary peripheral clock frequency 100 MHz
VCLK2 - Secondary peripheral clock
f
VCLK2
100 MHz
frequency
VCLK3 - Secondary peripheral clock
f
VCLK3
100 MHz
frequency
VCLK4 - Secondary peripheral clock
f
VCLK4
150 MHz
frequency
VCLKA1 - Primary asynchronous
f
VCLKA1
100 MHz
peripheral clock frequency
VCLKA2 - Secondary asynchronous
f
VCLKA2
100 MHz
peripheral clock frequency
VCLKA3 - Primary asynchronous
f
VCLKA3
100 MHz
peripheral clock frequency
VCLKA4 - Secondary asynchronous
f
VCLKA4
100 MHz
peripheral clock frequency
f
RTICLK
RTICLK - clock frequency f
VCLK
MHz
5.6 Wait States Required
Figure 5-1. Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined
mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and
180 MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
Copyright © 2012–2015, Texas Instruments Incorporated Specifications 43
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