Datasheet

HTU1 HTU2
Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
CRC
Switched Central Resource
Peripheral Central Resource Bridge
Dual Cortex-R4F
CPUs in Lockstep
Switched Central Resource
DCAN1
DCAN2
DCAN3
LIN
SCI
SPI4
64 KB Flash
for EEPROM
Emulation
with ECC
MibSPI1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MibSPI3
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MibSPI5
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN_TX
SCI_RX
SCI_TX
IOMM
PMM
VIM
RTI
DCC1
DCC2
32K
32K
32K
192kB RAM
with ECC
DMA POM
# 2
# 3
# 5
# 1
# 2
# 1
always on
Core/RAM
RAM
Core
Color Legend for Power Domains
SYS
nPORRST
nRST
ECLK
ESM
nERROR
1.25MB
Flash
with
ECC
32K
32K
32K
Switched Central Resource
I2C
N2HET1
GIO
I2C_SCL
I2C_SDA
GIOB[7:0] GIOA[7:0]
N2HET2[18,16]
N2HET2[15:0] N2HET1[31:0]
N2HET1_PIN_nDIS N2HET2_PIN_nDIS
N2HET2
MibADC1 MibADC2
AD1EVT
AD1IN[7:0]
AD2EVT
VSSAD
VCCAD
ADREFHI
ADREFLO
AD1IN[15:8] \
AD2IN[15:8]
AD1IN[23:16] \
AD2IN[7:0]
EMIF
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[12:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nWAIT
eQEP
1,2
eQEPxA
eQEPxB
eQEPxS
eQEPxI
eCAP
1..6
eCAP[6:1]
ePWM
1..7
nTZ[3:1]
SYNCO
SYNCI
ePWMxA
ePWMxB
MIBSPI5_CLK
TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
1.4 Functional Block Diagram
NOTE
The block diagram reflects the 337BGA package. Some pins are multiplexed or not available
in the 144QFP. For details, see the respective terminal functions tables in Section 4.3.
Figure 1-1. Functional Block Diagram
4 Device Overview Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS570LS1224