Datasheet
TMS570LS1224
www.ti.com
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015
4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-31. ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal Signal Reset Pull Pull Type Description
Type State
Signal Name 337
ZWT
MIBSPI1CLK F18 I/O Pull Up Programmable, MibSPI1 clock, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 R2 MibSPI1 chip select, or
GPIO
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S F3
MIBSPI1NCS[2]/N2HET1[19] G3
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 Pull Down Programmable, MibSPI1 chip select, or
20 µA GPIO
N2HET1[24]/MIBSPI1NCS[5] P1
MIBSPI1NENA/N2HET1[23]/ECAP4 G19 Pull Up Programmable, MibSPI1 enable, or GPIO
20 µA
MIBSPI1SIMO[0] F19 MibSPI1 slave-in master-
out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1] E18 Pull Down Programmable, MibSPI1 slave-in master-
20 µA out, or GPIO
MIBSPI1SOMI[0] G18 Pull Up Programmable, MibSPI1 slave-out master-
20 µA in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 R2
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 I/O Pull Up Programmable, MibSPI3 clock, or GPIO
20 µA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ V10 MibSPI3 chip select, or
EQEP1I/N2HET2_PIN_nDIS GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3 Pull Down Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Pull Up Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 MibSPI3 slave-in master-
out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 MibSPI3 slave-out master-
in, or GPIO
MIBSPI5CLK H19 I/O Pull Up Programmable, MibSPI5 clock, or GPIO
20 µA
MIBSPI5NCS[0]/EPWM4A E19 MibSPI5 chip select, or
GPIO
MIBSPI5NCS[1] B6
MIBSPI5NCS[2] W6
MIBSPI5NCS[3] T12
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 H18 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] J19 MibSPI5 slave-in master-
out, or GPIO
MIBSPI5SIMO[1] E16
MIBSPI5SIMO[2] H17
MIBSPI5SIMO[3] G17
MIBSPI5SOMI[0] J18 MibSPI5 slave-out master-
in, or GPIO
MIBSPI5SOMI[1] E17
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 H18
MIBSPI5SOMI[2] H16
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] J19
MIBSPI5SOMI[3] G16
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