Datasheet

TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-12. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal Signal Reset Pull Pull Type Description
Type State
Signal Name 144
PGE
MIBSPI1CLK 95 I/O Pull Up Programmable, MibSPI1 clock, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 MibSPI1 chip select, or
GPIO
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S 130
MIBSPI1NCS[2]/N2HET1[19] 40
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 Pull Down Programmable, MibSPI1 chip select, or
20 µA GPIO
N2HET1[24]/MIBSPI1NCS[5] 91
MIBSPI1NENA/N2HET1[23]/ECAP4 96 Pull Up Programmable, MibSPI1 enable, or GPIO
20 µA
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-
out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1] 106 Pull Down Programmable, MibSPI1 slave-in master-
20 µA out, or GPIO
MIBSPI1SOMI[0] 94 Pull Up Programmable, MibSPI1 slave-out master-
20 µA in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 I/O Pull Up Programmable, MibSPI3 clock, or GPIO
20 µA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ 55 MibSPI3 chip select, or
EQEP1I/N2HET2_PIN_nDIS GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 Pull Down Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pull Up Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-in master-
out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-out master-
in, or GPIO
MIBSPI5CLK 100 I/O Pull Up Programmable, MibSPI5 clock, or GPIO
20 µA
MIBSPI5NCS[0]/EPWM4A 32 MibSPI5 chip select, or
GPIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5 97 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 slave-in master-
out, or GPIO
MIBSPI5SOMI[0] 98 MibSPI5 slave-out master-
in, or GPIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5 97 MibSPI5 slave-out master-
in, or GPIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 slave-out master-
in, or GPIO
18 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated
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