Datasheet

TMS570LS1224
www.ti.com SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015
8.6 Device Identification
8.6.1 Device Identification Code Register
The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Table 8-1. The device identification code
register value for this device is:
• Rev A = 0x8046AD05
• Rev B = 0x8046AD15
• Rev C = 0x8046AD1D
Figure 8-2. Device ID Bit Allocation Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP-15 UNIQUE ID TECH
R-1 R-00000000100011 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TECH I/O PERIPH FLASH ECC RAM VERSION 1 0 1
VOLT PARITY ECC
AGE
R-101 R-0 R-1 R-10 R-1 R-00011 R-1 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-1. Device ID Bit Allocation Register Field Descriptions
Bit Field Value Description
31 CP15 Indicates the presence of coprocessor 15
1 CP15 present
30-17 UNIQUE ID 100011 Unique device identification number
This bitfield holds a unique number for a dedicated device configuration (die).
16-13 TECH Process technology on which the device is manufactured.
0101 F021
12 I/O VOLTAGE I/O voltage of the device.
0 I/O are 3.3v
11 PERIPHERAL 1 Peripheral Parity
PARITY Parity on peripheral memories
10-9 FLASH ECC Flash ECC
10 Program memory with ECC
8 RAM ECC Indicates if RAM memory ECC is present.
1 ECC implemented
7-3 REVISION Revision of the Device.
2-0 101 The platform family ID is always 0b101
8.6.2 Die Identification Registers
The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit dieid with the
information as shown in Table 8-2.
Table 8-2. Die-ID Registers
Item # of Bits Bit Location
X Coordinate on Wafer 12 0xFFFFFF7C[11:0]
Y Coordinate on Wafer 12 0xFFFFFF7C[23:12]
Wafer # 8 0xFFFFFF7C[31:24]
Lot # 24 0xFFFFFF80[23:0]
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