Datasheet

V
S1
On-State
Bias Current
Off-State
Leakages
V
S2
V
S24
I
AOSB
I
AIL
I
AIL
R
ext
R
ext
R
ext
P
in
S
mux
R
mux
P
in
S
mux
R
mux
P
in
S
mux
R
mux
S
samp
R
samp
C
samp
C
ext
I
AIL
I
AIL
I
AIL
I
AIL
C
mux
C
ext
C
ext
TMS570LS1224
SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015 www.ti.com
Figure 7-6. MibADC Input Equivalent Circuit
Table 7-21. MibADC Timing Specifications
Parameter MIN NOM MAX Unit
t
c(ADCLK)
(1)
Cycle time, MibADC clock 0.033 µs
t
d(SH)
(2)
Delay time, sample and hold 0.2 µs
time
t
d(PU-ADV)
Delay time from ADC power on 1 µs
until first input can be sampled
12-bit mode
t
d©)
Delay time, conversion time 0.4 µs
t
d(SHC)
(3)
Delay time, total sample/hold 0.6 µs
and conversion time
10-bit mode
t
d©)
Delay time, conversion time 0.33 µs
t
d(SHC)
(3)
Delay time, total sample/hold 0.53 µs
and conversion time
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the ADC’s internal impedance.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for
example, the prescale settings.
126 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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