Datasheet

TMS570LS1224
www.ti.com SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015
7.4.3 ADC Electrical and Timing Specifications
Table 7-19. MibADC Recommended Operating Conditions
Parameter MIN MAX Unit
AD
REFHI
A-to-D high-voltage reference source AD
REFLO
V
CCAD
(1)
V
AD
REFLO
A-to-D low-voltage reference source V
SSAD
(1)
AD
REFHI
V
V
AI
Analog input voltage AD
REFLO
AD
REFHI
V
I
AIK
Analog input clamp current
(2)
- 2 2 mA
(V
AI
< V
SSAD
– 0.3 or V
AI
> V
CCAD
+ 0.3)
(1) For V
CCAD
and V
SSAD
recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 7-20. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions
Parameter Description/Conditions MIN Nom MAX Unit
R
mux
Analog input mux on- See Figure 7-6 250 Ω
resistance
R
samp
ADC sample switch on- See Figure 7-6 250 Ω
resistance
C
mux
Input mux capacitance See Figure 7-6 16 pF
C
samp
ADC sample capacitance See Figure 7-6 13 pF
I
AIL
Analog off-state input V
CCAD
= 3.6V V
SSAD
≤ V
IN
< V
SSAD
+ 100mV -300 200 nA
leakage current maximum
V
SSAD
+ 100mV ≤ V
IN
≤ V
CCAD
- 200mV -200 200 nA
V
CCAD
- 200mV < V
IN
≤ V
CCAD
-200 500 nA
I
AIL
Analog off-state input V
CCAD
= 5.5V V
SSAD
≤ V
IN
< V
SSAD
+ 300mV -1000 250 nA
leakage current maximum
V
SSAD
+ 300mV ≤ V
IN
≤ V
CCAD
- 300mV -250 250 nA
V
CCAD
- 300mV < V
IN
≤ V
CCAD
-250 1000 nA
I
AOSB1
(1)
ADC1 Analog on-state input V
CCAD
= 3.6V V
SSAD
≤ V
IN
< V
SSAD
+ 100mV -8 2 µA
bias current maximum
V
SSAD
+ 100mV < V
IN
< V
CCAD
- 200mV -4 2 µA
V
CCAD
- 200mV < V
IN
< V
CCAD
-4 12 µA
I
AOSB2
(1)
ADC2 Analog on-state input V
CCAD
= 3.6V V
SSAD
≤ V
IN
< V
SSAD
+ 100mV -7 2 µA
bias current maximum
V
SSAD
+ 100mV ≤ V
IN
≤ V
CCAD
- 200mV -4 2 µA
V
CCAD
- 200mV < V
IN
≤ V
CCAD
-4 10 µA
I
AOSB1
(1)
ADC1 Analog on-state input V
CCAD
= 5.5V V
SSAD
≤ V
IN
< V
SSAD
+ 300mV -10 3 µA
bias current maximum
V
SSAD
+ 300mV ≤ V
IN
≤ V
CCAD
- 300mV -5 3 µA
V
CCAD
- 300mV < V
IN
≤ V
CCAD
-5 14 µA
I
AOSB2
(1)
ADC2 Analog on-state input V
CCAD
= 5.5V V
SSAD
≤ V
IN
< V
SSAD
+ 300mV -8 3 µA
bias current maximum
V
SSAD
+ 300mV ≤ V
IN
≤ V
CCAD
- 300mV -5 3 µA
V
CCAD
- 300mV < V
IN
≤ V
CCAD
-5 12 µA
I
ADREFHI
AD
REFHI
input current AD
REFHI
= V
CCAD
, AD
REFLO
= V
SSAD
3 mA
I
CCAD
Static supply current Normal operating mode 15 mA
ADC core in power down mode 5 µA
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to I
AOSB1
+ I
AOSB2
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