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TMS570LS1224

SPNS190B –OCTOBER 2012–REVISED FEBRUARY 2015

TMS570LS1224 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1 Features

• High-Performance Automotive-Grade • Enhanced Timing Peripherals for Motor Control

Microcontroller for Safety-Critical Applications

– 7 Enhanced Pulse Width Modulator (ePWM)

– Dual CPUs Running in Lockstep Modules

– ECC on Flash and RAM Interfaces – 6 Enhanced Capture (eCAP) Modules

– Built-In Self-Test (BIST) for CPU and On-chip – 2 Enhanced Quadrature Encoder Pulse (eQEP)

RAMs Modules

– Error Signaling Module With Error Pin • Two Next Generation High-End Timer (N2HET)

Modules

– Voltage and Clock Monitoring

– N2HET1: 32 Programmable Channels

• ARM

Cortex

-R4F 32-Bit RISC CPU

– N2HET2: 18 Programmable Channels

– 1.66 DMIPS/MHz With 8-Stage Pipeline

– 160-Word Instruction RAM Each With Parity

– FPU With Single- and Double-Precision

Protection

– 12-Region Memory Protection Unit (MPU)

– Each N2HET Includes Hardware Angle

– Open Architecture With Third-Party Support

Generator

• Operating Conditions

– Dedicated High-End Timer Transfer Unit (HTU)

– Up to 180-MHz System Clock

for Each N2HET

– Core Supply Voltage (VCC): 1.14 to 1.32 V

• Two 12-Bit Multibuffered Analog-to-Digital

– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

Converter (MibADC) Modules

• Integrated Memory

– ADC1: 24 Channels

– 1.25MB of Program Flash With ECC

– ADC2: 16 Channels Shared With ADC1

– 192KB of RAM With ECC

– 64 Result Buffers Each With Parity Protection

– 64KB of Flash for Emulated EEPROM With

• Multiple Communication Interfaces

ECC

– Three CAN Controllers (DCANs)

• 16-Bit External Memory Interface (EMIF)

• 64 Mailboxes Each With Parity Protection

• Common Platform Architecture

• Compliant to CAN Protocol Version 2.0A and

– Consistent Memory Map Across Family

2.0B

– Real-Time Interrupt (RTI) Timer (OS Timer)

– Inter-Integrated Circuit (I

– 128-Channel Vectored Interrupt Module (VIM)

– Three Multibuffered Serial Peripheral Interface

– 2-Channel Cyclic Redundancy Checker (CRC)

(MibSPI) Modules

• Direct Memory Access (DMA) Controller

• 128 Words Each With Parity Protection

– 16 Channels and 32 Control Packets

• 8 Transfer Groups

– Parity Protection for Control Packet RAM

– Up to Two Standard Serial Peripheral Interface

– DMA Accesses Protected by Dedicated MPU

(SPI) Modules

• Frequency-Modulated Phase-Locked Loop

– Two UART (SCI) Interfaces, One With Local

(FMPLL) With Built-In Slip Detector

Interconnect Network (LIN 2.1) Interface

Support

• Separate Nonmodulating PLL

• Packages

• IEEE 1149.1 JTAG, Boundary Scan and ARM

CoreSight™ Components

– 144-Pin Quad Flatpack (PGE) [Green]

• Advanced JTAG Security Module (AJSM)

– 337-Ball Grid Array (ZWT) [Green]

• Calibration Capabilities

– Parameter Overlay Module (POM)

• 16 General-Purpose Input/Output (GPIO) Pins

Capable of Generating Interrupts

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (172 pages)

PAGE 1
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 TMS570LS1224 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 1.2 • • • • Applications Braking Systems (ABS and ESC) Electric Power Steering (EPS) HEV and EV Inverter Systems Battery Management Systems 1.3 www.ti.com • • • • Active Driver Assistance Systems Aerospace and Avionics Railway Communications Off-road Vehicles Description The TMS570LS1224 device is a high-performance automotive-grade microcontroller family for safety systems.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. Each MibADC supports three separate groupings of channels. Each group can be converted once when triggered or configured for continuous conversion mode.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 1.4 www.ti.com Functional Block Diagram NOTE The block diagram reflects the 337BGA package. Some pins are multiplexed or not available in the 144QFP. For details, see the respective terminal functions tables in Section 4.3. 192kB RAM with ECC 32K 32K 32K 32K 32K 32K 1.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table of Contents 1 2 3 4 5 Device Overview ......................................... 1 Device Memory Map Features .............................................. 1 6.10 Flash Memory ....................................... 75 1.2 Applications ........................................... 2 6.11 Tightly Coupled RAM Interface Module ............. 78 1.3 Description ............................................ 2 6.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 2 Revision History This data manual revision history highlights the technical changes made to the SPNS190A device-specific data manual addendum to make it an SPNS190B revision. Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS1224 devices, which are now in the production data (PD) stage of development have been incorporated.
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TMS570LS1224 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Changed EMIF th(EMOEH-EMCEH) from +4 to +5 .................................................................................... 85 Changed EMIF tsu(EMBAV-EMOEL) from (RS)*E-5 to (RS)*E-6..................................................................... 85 Changed EMIF th(EMOEH-EMBAIV) from (RS)*E-4 to (RS)*E-3 ..........................................................
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 3 Device Comparison Table 3-1 lists the features of the TMS570LS1224 devices. Table 3-1.
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TMS570LS1224 www.ti.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.2 www.ti.
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TMS570LS1224 www.ti.com 4.3 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Terminal Functions Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a functional pin/ball description.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 4-1.
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TMS570LS1224 www.ti.com 4.3.1.2 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Enhanced High-End Timer Modules (N2HET) Table 4-2.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 4-2.
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TMS570LS1224 www.ti.com 4.3.1.4 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Enhanced Quadrature Encoder Pulse Modules (eQEP) Table 4-4.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM) (continued) Terminal Signal Name 144 PGE MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 N2HET1[10]/nTZ3 4.3.1.6 Signal Type Reset Pull State Pull Type Description Input Pull Up Fixed 20 µA Pull Up Trip Zone Inputs 1, 2 and 3.
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TMS570LS1224 www.ti.com 4.3.1.8 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Local Interconnect Network Interface Module (LIN) Table 4-8. PGE Local Interconnect Network Interface Module (LIN) Terminal Signal Name 144 PGE LINRX 131 LINTX 132 4.3.1.9 Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description LIN receive, or GPIO LIN transmit, or GPIO Standard Serial Communication Interface (SCI) Table 4-9.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI) Table 4-12.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.1.13 System Module Interface Table 4-13. PGE System Module Interface Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description nPORRST 46 Input Pull Down Fixed 100 µA Pull Down Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.1.15 Test and Debug Modules Interface Table 4-15. PGE Test and Debug Modules Interface Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description Input Pull Down Fixed 100 µA Pull Down Test enable. This terminal must be connected to ground directly or via a pull-down resistor.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.1.17 Supply for Core Logic: 1.2V nominal Table 4-17. PGE Supply for Core Logic: 1.2V nominal Terminal Signal Name 144 PGE VCC 17 VCC 29 VCC 45 VCC 48 VCC 49 VCC 57 VCC 87 VCC 101 VCC 114 VCC 123 VCC 137 VCC 143 Signal Type Reset Pull State Pull Type 1.2V Power N/A None Description Core supply 4.3.1.18 Supply for I/O Cells: 3.3V nominal Table 4-18. PGE Supply for I/O Cells: 3.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.1.19 Ground Reference for All Supplies Except VCCAD Table 4-19.
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TMS570LS1224 www.ti.com 4.3.2 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 ZWT Package 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC) Table 4-20.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.2 www.ti.com Enhanced High-End Timer Modules (N2HET) Table 4-21.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 4-21.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.3 www.ti.com Enhanced Capture Modules (eCAP) Table 4-22.
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TMS570LS1224 www.ti.com 4.3.2.5 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Enhanced Pulse-Width Modulator Modules (ePWM) Table 4-24.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.6 www.ti.com General-Purpose Input / Output (GPIO) Table 4-25.
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TMS570LS1224 www.ti.com 4.3.2.7 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Controller Area Network Controllers (DCAN) Table 4-26. ZWT Controller Area Network Controllers (DCAN) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description CAN1RX B10 CAN1TX A10 CAN2RX H1 CAN2 receive, or GPIO CAN2TX H2 CAN2 transmit, or GPIO CAN3RX M19 CAN3 receive, or GPIO CAN3TX M18 CAN3 transmit, or GPIO 4.3.2.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C) Table 4-29. ZWT Inter-Integrated Circuit Interface Module (I2C) Terminal Signal Name 337 ZWT MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description I2C serial data, or GPIO I2C serial clock, or GPIO 4.3.2.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI) Table 4-31.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.13 External Memory Interface (EMIF) Table 4-32. External Memory Interface (EMIF) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description Pull Up None EMIF Clock Enable None EMIF clock. This is an output signal in functional mode. It is gated off by default, so that the signal is pulled up. PINMUX29[8] must be cleared to enable this output.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 4-32.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.14 System Module Interface Table 4-33. ZWT System Module Interface Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description nPORRST W7 Input Pull Down Fixed 100 µA Pull Down Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.16 Test and Debug Modules Interface Table 4-35. ZWT Test and Debug Modules Interface Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description Input Pull Down Fixed 100 µA Pull Down Test enable. This terminal must be connected to ground directly or via a pull-down resistor.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.19 No Connects Table 4-38. No Connects Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 4-38. No Connects (continued) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.20 Supply for Core Logic: 1.2V nominal Table 4-39. ZWT Supply for Core Logic: 1.2V nominal Terminal Signal Name 337 ZWT VCC F9 VCC F10 VCC H10 VCC J14 VCC K6 VCC K8 VCC K12 VCC K14 VCC L6 VCC M10 VCC P10 38 Signal Type Reset Pull State Pull Type 1.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.21 Supply for I/O Cells: 3.3V nominal Table 4-40. ZWT Supply for I/O Cells: 3.3V nominal Terminal Signal Name 337 ZWT VCCIO F6 VCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 VCCIO L14 VCCIO M6 VCCIO M14 VCCIO N6 VCCIO N14 VCCIO P6 VCCIO P7 VCCIO P8 VCCIO P9 VCCIO P12 VCCIO P13 VCCIO P14 Signal Type Reset Pull State Pull Type 3.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.22 Ground Reference for All Supplies Except VCCAD Table 4-41.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 5 Specifications 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range VCC (2) Supply voltage range: VCCIO, VCCP Input voltage range: Input clamp current: (2) (1) MIN MAX UNIT -0.3 1.43 V -0.3 4.6 V VCCAD -0.3 6.25 V All input pins, with exception of ADC pins -0.3 4.6 V ADC input pins -0.3 6.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Device Recommended Operating Conditions (1) 5.4 MIN NOM MAX UNIT VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V VCCPLL PLL Supply Voltage 1.14 1.2 1.32 V VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V VCCAD MibADC supply voltage 3 5.25 V VCCP Flash pump supply voltage 3 3.
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TMS570LS1224 www.ti.com 5.5 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Switching Characteristics Over Recommended Operating Conditions for Clock Domains Table 5-1.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 5.7 www.ti.
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TMS570LS1224 www.ti.com 5.8 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Input/Output Electrical Characteristics Over Recommended Operating Conditions (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vhys Input hysteresis All inputs 180 mV VIL Low-level input voltage All inputs -0.3 0.8 V VIH High-level input voltage All inputs 2 VCCIO + 0.3 V IOL = IOLmax VOL Low-level output voltage IOL = 50 µA, standard output mode 0.2 IOL = 50 µA, low-EMI output mode (see Section 5.13) 0.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 5-3. Thermal Resistance Characteristics (ZWT Package) (continued) °C/W Junction-to-package top, Still air (includes 5x5 thermal via cluster in 2s2p PCB connected to 1st ground plane) ΨJT 0.33 5.10 Output Buffer Drive Strengths Table 5-4.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 5-5. Selectable 8 mA/2 mA Control (continued) (1) Signal Control Bit Address 8 mA 2 mA SPI2SOMI SPI2PC9[11] (1) 0xFFF7 F668 0 1 Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits differ, SPI2PC9[11] determines the drive strength. 5.11 Input Timings t pw Input V IH VCCIO VIH VIL V IL 0 Figure 5-2. TTL-Level Inputs Table 5-6.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 5-7.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 5.13 Low-EMI Output Buffers The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6 System Information and Electrical Specifications 6.1 Device Power Domains The device core logic is split up into multiple power domains to optimize the Self-Test Clock Configuration power for a given application use case. There are 7 power domains in total: PD1, PD2, PD3, PD5, RAM_PD1, and RAM_PD2. Refer to Section 1.4 for more information. PD1 is an "always-ON" power domain, which cannot be turned off.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-1. Voltage Monitoring Specifications PARAMETER VMON 6.2.3 Voltage monitoring thresholds MIN TYP MAX UNIT VCC low - VCC level below this threshold is detected as too low. 0.75 0.9 1.13 V VCC high - VCC level above this threshold is detected as too high. 1.40 1.7 2.1 VCCIO low - VCCIO level below this threshold is detected as too low. 1.85 2.4 2.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.3 www.ti.com Power Sequencing and Power On Reset 6.3.1 Power-Up Sequence There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The powerup sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-4. Electrical Requirements for nPORRST (continued) NO Parameter tf(nPORRST) Filter time nPORRST pin; MIN MAX Unit 475 2000 ns pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset. 3.3 V 1.2 V VCCIOPORH VCCPORH 6 VCCIOPORL VCC (1.2 V) VCCIO / VCCP(3.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.4 www.ti.com Warm Reset (nRST) This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only).
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TMS570LS1224 www.ti.com 6.5 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 ARM Cortex-R4F CPU Information 6.5.1 Summary of ARM Cortex-R4F CPU Features The features of the ARM Cortex-R4F CPU include: • An integer unit with integral Embedded ICE-RT logic. • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.5.4 www.ti.com Duplicate clock tree after GCLK The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit.
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TMS570LS1224 www.ti.com 6.5.6.1 1. 2. 3. 4. 5. 6. 7. SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Application Sequence for CPU Self-Test Configure clock domain frequencies. Select number of test intervals to be run. Configure the timeout period for the self-test run. Enable self-test. Wait for CPU reset. In the reset handler, read CPU self-test status to identify any failures. Retrieve CPU state if required. For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515). 6.5.6.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6 www.ti.com Clocks 6.6.1 Clock Sources The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source. The table also shows the default state of each clock source. Table 6-8.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.1.1.1 Timing Requirements for Main Oscillator Table 6-9.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.1.2 www.ti.com Low Power Oscillator The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro. 6.6.1.2.1 Features The main features of the LPO are: • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module. • Supplies a high-frequency clock for non-timing-critical systems.
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TMS570LS1224 www.ti.com 6.6.1.3 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Phase Locked Loop (PLL) Clock Modules The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled. • Configurable frequency multipliers and dividers. • Built-in PLL Slip monitoring circuit.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.1.4 www.ti.com External Clock Inputs The device supports up to two external clock inputs. This clock input must be a square wave input. The electrical and timing requirements for these clock inputs are specified below. The external clock sources are not checked for validity. They are assumed valid when enabled. Table 6-12.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-13.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.2.2 www.ti.com Mapping of Clock Domains to Device Modules Each clock domain has a dedicated functionality as shown in the figures below. GCM 0 OSCIN PLL #1 /1..64 X1..256 Low Power Oscillator PLL #2 /1..64 X1..256 * the frequency at this node must not exceed the maximum HCLK specifiation. GCLK, GCLK2 (to CPU) (FMzPLL) /1..32 /1..8 1 * 80kHz 4 10MHz /1..
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TMS570LS1224 www.ti.com 6.6.3 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Clock Test Mode The platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. Table 6-14.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.7 www.ti.com Clock Monitoring The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO). The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO). The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN).
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-15. DCC1 Counter 0 Clock Sources (continued) CLOCK SOURCE [3:0] CLOCK NAME 0xA test clock (TCK) Table 6-16.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.8 www.ti.com Glitch Filters A glitch filter is present on the following signals. Table 6-19.
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TMS570LS1224 www.ti.com 6.9 6.9.1 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Device Memory Map Memory Map Diagram The figure below shows the device memory map.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.9.2 www.ti.com Memory Map Table Table 6-20. Device Memory Map FRAME ADDRESS RANGE MODULE NAME FRAME CHIP SELECT TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 1.25MB TCM RAM + RAM ECC CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 192KB Mirrored Flash Flash mirror frame 0x2000_0000 0x20FF_FFFF 16MB 1.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-20.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-20.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-20.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-21.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.10 Flash Memory 6.10.1 Flash Memory Configuration Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic. Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.10.3 ECC Protection for Flash Accesses All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.10.5 Program Flash Table 6-23. Timing Requirements for Program Flash Parameter MIN tprog(144bit) Wide Word (144bit) programming time tprog(Total) 1.25MByte programming time (1) terase(bank0) (1) (2) MAX Unit 40 300 µs 13 s 6.6 s -40°C to 125°C Sector/Bank erase time (2) 0°C to 60°C, for first 25 cycles 3.3 -40°C to 125°C 0.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.11 Tightly Coupled RAM Interface Module Figure 6-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.13 On-Chip SRAM Initialization and Testing 6.13.1 On-Chip SRAM Self-Test Using PBIST 6.13.1.1 Features • • • Extensive instruction set to support various memory test algorithms ROM-based algorithms allow application to run TI production-level memory tests Independent testing of all on-chip SRAM 6.13.1.2 PBIST RAM Groups Table 6-25.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.13.2 On-Chip SRAM Auto Initialization This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.14 External Memory Interface (EMIF) 6.14.1 Features The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices.
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TMS570LS1224 www.ti.com EMIF_nCS[3:2] SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 SETUP Extended Due to EMIF_WAIT STROBE STROBE HOLD EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DATA[15:0] 14 11 EMIF_nOE 2 2 EMIF_WAIT Asserted Deasserted Figure 6-12. EMIFnWAIT Read Timing Requirements 15 1 EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_nDQM[1:0] 16 17 18 19 20 21 24 22 23 EMIF_nWE 27 26 EMIF_DATA[15:0] EMIF_nOE Figure 6-13.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 SETUP www.ti.com Extended Due to EMIF_WAIT STROBE STROBE HOLD EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DATA[15:0] 28 25 EMIF_nWE 2 EMIF_WAIT 2 Deasserted Asserted Figure 6-14. EMIFnWAIT Write Timing Requirements Table 6-27. EMIF Asynchronous Memory Timing Requirements (1) NO.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-28.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-28.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.14.2.2 Synchronous Timing BASIC SDRAM READ OPERATION 1 2 2 EMIF_CLK 4 3 EMIF_nCS[0] 6 5 EMIF_nDQM[1:0] 7 8 7 8 EMIF_BA[1:0] EMIF_ADDR[12:0] 19 2 EM_CLK Delay 17 20 18 EMIF_DATA[15:0] 11 12 EMIF_nRAS 13 14 EMIF_nCAS EMIF_nWE Figure 6-15.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com BASIC SDRAM WRITE OPERATION 1 2 2 EMIF_CLK 4 3 EMIF_CS[0] 6 5 EMIF_DQM[1:0] 7 8 7 8 EMIF_BA[1:0] EMIF_ADDR[12:0] 9 10 EMIF_DATA[15:0] 11 12 EMIF_nRAS 13 EMIF_nCAS 15 16 EMIF_nWE Figure 6-16. Basic SDRAM Write Operation Table 6-29. EMIF Synchronous Memory Timing Requirements NO.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-30. EMIF Synchronous Memory Switching Characteristics (continued) NO.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.15 Vectored Interrupt Manager The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-31.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-31.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels. NOTE The application can change the mapping of interrupt sources to the interrupt channels through the interrupt channel control registers (CHANCTRLx) inside the VIM module.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.16 DMA Controller The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to: • Transfer blocks of data between external and internal data memories • Restructure portions of internal data memory • Continually service a peripheral 6.16.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.16.2 Default DMA Request Map The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on. Some DMA requests have multiple sources, as shown in Table 6-32.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.17 Real Time Interrupt Module The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the timebases needed for scheduling an operating system.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 31 0 Update compare RTIUDCPy + 31 0 Compare DMAREQy RTICOMPy From counter block 0 = INTy From counter block 1 Compare control Figure 6-18. Compare Block Diagram 6.17.3 Clock Source Options The RTI module uses the RTI1CLK clock domain for generating the RTI time bases. The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.18 Error Signaling Module The Error Signaling Module (ESM) manages the various error conditions on the microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an indicator to an external monitor circuit to put the system into a safe state. 6.18.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-35.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-35.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-35.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.19 Reset / Abort / Error Sources Table 6-36. Reset/Abort/Error Sources ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-36. Reset/Abort/Error Sources (continued) ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.channel ESM 1.7 ESM 1.34 N2HET1 Memory parity error User/Privilege N2HET2 Memory parity error User/Privilege MIBSPI MibSPI1 memory parity error User/Privilege ESM 1.17 MibSPI3 memory parity error User/Privilege ESM 1.18 User/Privilege ESM 1.24 User/Privilege ESM 1.19 User/Privilege ESM 1.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-36. Reset/Abort/Error Sources (continued) SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.20 Digital Windowed Watchdog This device includes a digital windowed watchdog (DWWD) module that protects against runaway code execution. The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.21 Debug Subsystem 6.21.1 Block Diagram The device contains an ICEPICK module to allow JTAG access to the scan chains. Boundary Scan BSR/BSDL Boundary Scan I/F TRST TMS TCK RTCK TDI TDO Debug ROM1 Debug APB DAP Secondary Tap 0 APB Mux AHB-AP POM ICEPICK_C to SCR1 via A2A from PCR1/Bridge APB slave Cortex R4F Secondary Tap 2 AJSM Test Tap 0 eFuse Farm Test Tap 1 PSCON Figure 6-19. Debug Subsystem Block Diagram 6.21.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.21.4 Debug ROM The Debug ROM stores the location of the components on the Debug APB bus: Table 6-39.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.21.5 JTAG Scan Interface Timings Table 6-40. JTAG Scan Interface Timing (1) No.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.21.6 Advanced JTAG Security Module This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the device’s memory content by allowing users to secure the device after programming. Flash Module Output OTP Contents (example) H L H ... ...
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.21.7 Boundary Scan Chain The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module. Device Pins (conceptual) RTCK TDI TDO IC E P ICK TRST TMS TCK Boundary Scan Interface Boundary Scan TDI TDO BSDL Figure 6-22.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7 Peripheral Information and Electrical Specifications 7.1 Enhanced Translator PWM Modules (ePWM) Figure 7-1 illustrates the connections between the seven ePWM modules (ePWM1,2,3,4,5,6,7) on the device.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.1.1 www.ti.com ePWM Clocking and Reset Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active low, the clock enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected. Table 7-1.
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TMS570LS1224 www.ti.com 7.1.4 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is implemented as PINMMR37 register bit 1. When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default condition. When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-3.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-5. ePWMx Switching Characteristics (continued) PARAMETER td(TZ- TEST CONDITIONS MIN Delay time, trip input active to PWM Hi-Z MAX UNIT 20 ns MAX UNIT PWM)HZ Table 7-6.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.2 www.ti.com Enhanced Capture Modules (eCAP) Figure 7-3 shows how the eCAP modules are interconnected on this microcontroller. EPWM1SYNCO ECAP1SYNCI ECAP1 VIM ECAP1INTn ECAP1 VBus32 VCLK4, SYS_nRST ECAP1ENCLK ECAP1SYNCO ECAP2SYNCI VIM ECAP2INTn ECAP 2/3/4/5 IOMUX ECAP2 VBus32 VCLK4, SYS_nRST ECAP2SYNCO ECAP2ENCLK ECAP6 VIM ECAP6INTn ECAP 6 VBus32 VCLK4, SYS_nRST ECAP6ENCLK Figure 7-3. eCAP Module Connections 7.2.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-7. eCAPx Clock Enable Control ePWM Module Instance Control Register to Enable Clock Default Value eCAP1 PINMMR39[0] 1 eCAP2 PINMMR39[8] 1 eCAP3 PINMMR39[16] 1 eCAP4 PINMMR39[24] 1 eCAP5 PINMMR40[0] 1 eCAP6 PINMMR40[8] 1 The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that the VCLK4 clock connections to the eCAPx modules are enabled by default.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.3 www.ti.com Enhanced Quadrature Encoder (eQEP) Figure 7-4 shows the eQEP module interconnections on the device. VBus32 EQEP1A EQEP1B EQEP1ENCLK VCLK4 SYS_nRST EPWM1/..
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-12.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.4.1 www.ti.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE If ADEVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com NOTE If AD2EVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 SOCAEN, SOCBEN bits inside ePWMx modules Controlled by PINMMR EPWM1SOCA EPWM1 module EPWM1SOCB EPWM2SOCA EPWM2 module EPWM2SOCB EPWM3SOCA EPWM3 module EPWM3SOCB EPWM4SOCA EPWM4 module EPWM4SOCB EPWM5SOCA EPWM5 module EPWM5SOCB EPWM6SOCA EPWM6 module EPWM6SOCB EPWM7SOCA EPWM7 module EPWM7SOCB ePWM_B ePWM_A1 ePWM_A2 ePWM_AB Figure 7-5.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-18. Control Bit to SOC Output Control Bit SOC Output PINMMR35[0] SOC1A_SEL PINMMR35[8] SOC2A_SEL PINMMR35[16] SOC3A_SEL PINMMR35[24] SOC4A_SEL PINMMR36[0] SOC5A_SEL PINMMR36[8] SOC6A_SEL PINMMR36[16] SOC7A_SEL The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-5.
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TMS570LS1224 www.ti.com 7.4.3 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 ADC Electrical and Timing Specifications Table 7-19. MibADC Recommended Operating Conditions Parameter MIN MAX Unit (1) V V ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD ADREFLO A-to-D low-voltage reference source VSSAD (1) ADREFHI VAI Analog input voltage ADREFLO ADREFHI V IAIK Analog input clamp current (2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Rext Pin VS1 www.ti.com Smux Rmux Smux Rmux IAOSB Cext On-State Bias Current Rext Pin VS2 IAIL Cext IAIL IAIL Off-State Leakages Rext Pin Smux Rmux Ssamp Rsamp VS24 IAIL Csamp Cmux Cext IAIL IAIL Figure 7-6. MibADC Input Equivalent Circuit Table 7-21. MibADC Timing Specifications Parameter tc(ADCLK) (1) td(SH) (2) MIN Cycle time, MibADC clock Delay time, sample and hold time NOM MAX Unit 0.033 µs 0.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-22. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions (1) (2) Parameter Description/Conditions CR Conversion range over ADREFHI - ADREFLO which specified accuracy is maintained ZSET Zero Scale Offset FSET EDNL EINL Differential nonlinearity error Integral nonlinearity error ETOT (1) (2) Full Scale Offset Total unadjusted error MIN 3 Type MAX Unit 5.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.4.4 www.ti.com Performance (Accuracy) Specifications 7.4.4.1 MibADC Nonlinearity Errors The differential nonlinearity error shown in Figure 7-7 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (–½ LSB) 1 LSB 0 ... 010 Differential Linearity Error (–½ LSB) 0 ...
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 The integral nonlinearity error shown in Figure 7-8 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 0 ... 110 Ideal Transition Digital Output Code 0 ... 101 Actual Transition 0 ... 100 At Transition 011/100 (–½ LSB) 0 ... 011 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (–1/4 LSB) 0 ...
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.4.4.2 www.ti.com MibADC Total Error The absolute accuracy or total error of an MibADC as shown in Figure 7-9 is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (–1 1/4 LSB) 0 ... 011 0 ... 010 Total Error At Step 0 ... 001 (1/2 LSB) 0 ... 001 0 ...
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TMS570LS1224 www.ti.com 7.5 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 General-Purpose Input/Output The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable. Both GIOA and GIOB support external interrupt capability. 7.5.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.6 www.ti.com Enhanced High-End Timer (N2HET) The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O.
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TMS570LS1224 www.ti.com 7.6.3 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Input Timing Specifications All of the N2HET channels have an enhanced pulse capture circuit. The N2HET instructions PCNT and WCAP use this circuit to achieve the input timing requirements shown in Figure 7-10 and Table 7-23 below. 1 N2HETx 3 4 2 Figure 7-10. N2HET Input Capture Timings Table 7-23.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 N2HET1[1,3,5,7,9,11] www.ti.com IOMM mux control signal x N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18] N2HET1 N2HET2[8,10,12,14,16,18] N2HET2 Figure 7-12. N2HET Monitoring 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC) N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].
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TMS570LS1224 www.ti.com 7.6.7 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 High-End Timer Transfer Unit (HTU) A High End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU. 7.6.7.1 • • • • • • • • • 7.6.7.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.7 www.ti.com Controller Area Network (DCAN) The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps).
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TMS570LS1224 www.ti.com 7.8 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Local Interconnect Network Interface (LIN) The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility. The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.9 Serial Communication Interface (SCI) 7.9.1 Features • • • • • • • • • • • 138 www.ti.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.10 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module is a multi-master communication module providing an interface between the microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible device. 7.10.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.10.2 I2C I/O Timing Specifications Table 7-27. I2C Signals (SDA and SCL) Switching Characteristics (1) Parameter Standard Mode Fast Mode Unit MIN MAX MIN MAX 75.2 149 75.2 149 ns 0 100 0 400 kHz tc(I2CCLK) Cycle time, Internal Module clock for I2C, prescaled from VCLK f(SCL) SCL Clock frequency tc(SCL) Cycle time, SCL 10 2.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE • • • • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.11 Multibuffered / Standard Serial Peripheral Interface The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and analog-to-digital converters. 7.11.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.11.3.1 MIBSPI1 Event Trigger Hookup Table 7-30.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-31. MIBSPI3 Event Trigger Hookup (continued) Event # TGxCTRL TRIGSRC[3:0] Trigger EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 Internal Tick counter NOTE For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary).
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications Table 7-33. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. 1 2 (5) 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 SPISIMO 5 Master Out Data Is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 7-14. SPI Master Mode External Timing (CLOCK PHASE = 0) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-15.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-34. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 Master Out Data Is Valid SPISIMO 6 Data Valid 7 Master In Data Must Be Valid SPISOMI Figure 7-16. SPI Master Mode External Timing (CLOCK PHASE = 1) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-17.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.11.5 SPI Slave Mode I/O Timings Table 7-35. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI Data Is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-18. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn Figure 7-19.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-36. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI SPISOMI Data Is Valid 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-20. SPI Slave Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out Data Is Valid Figure 7-21.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 8 Device and Documentation Support 8.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (for example,TMS570LS1224). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS.
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TMS570LS1224 www.ti.com SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Full Part # TMS 570 Orderable Part # TMX 570 LS 12 2 4 B ZWT Q Q1 R 12 2 4 B ZWT Q Q1 R Prefix: TM TMS = Fully Qualified TMP = Prototype TMX = Samples Core Technology: 570 = Cortex R4F Architecture: LS = Dual CPUs in Lockstep (not included in orderable part #) Flash Memory Size: 12 = 1.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 8.2 8.2.1 www.ti.com Documentation Support Related Documentation from Texas Instruments The following documents describe the TMS570LS11x/12x microcontroller.. 8.2.2 SPNU515 TMS570LS12x/11x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.
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TMS570LS1224 www.ti.com 8.6 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Device Identification 8.6.1 Device Identification Code Register The device identification code register identifies several aspects of the device including the silicon version. The details of the device identification code register are shown in Table 8-1. The device identification code register value for this device is: • Rev A = 0x8046AD05 • Rev B = 0x8046AD15 • Rev C = 0x8046AD1D Figure 8-2.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 8-2.
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TMS570LS1224 www.ti.com 8.7 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 Module Certifications The following communications modules have received certification of adherence to a standard.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 8.7.1 www.ti.com DCAN Certification Figure 8-3.
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TMS570LS1224 www.ti.com 8.7.2 8.7.2.1 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 LIN Certification LIN Master Mode Figure 8-4.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 8.7.2.2 www.ti.com LIN Slave Mode - Fixed Baud Rate Figure 8-5.
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TMS570LS1224 www.ti.com 8.7.2.3 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 LIN Slave Mode - Adaptive Baud Rate Figure 8-6.
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TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 9 Mechanical Packaging and Orderable Information 9.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.