Datasheet

www.ti.com Control Registers and Control Packets
20.3.2.5 Element Index Offset Register (EIOFF)
Figure 20-118. Element Index Offset Register (EIOFF) [offset = 14h]
31 29 28 16
Reserved EIDXD
R-X R/WP-X
15 13 12 0
Reserved EIDXS
R-X R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 20-106. Element Index Offset Register (EIOFF) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reads are undefined. Writes have no effect.
28-16 EIDXD 0-1FFFh Destination address element index. These bits define the offset to be added to the
destination address after each element transfer.
15-13 Reserved 0 Reads are undefined. Writes have no effect.
12-0 EIDXS 0-1FFFh Source address element index. These bits define the offset to be added to the source
address after each element transfer.
20.3.2.6 Frame Index Offset Register (FIOFF)
Figure 20-119. Frame Index Offset Register (FIOFF) [offset = 18h]
31 29 28 16
Reserved FIDXD
R-X R/WP-X
15 13 12 0
Reserved FIDXS
R-X R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 20-107. Frame Index Offset Register (FIOFF) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reads are undefined. Writes have no effect.
28-16 FIDXD 0-1FFFh Destination address frame index. These bits define the offset to be added to the destination
address after element count reached one.
15-13 Reserved 0 Reads are undefined. Writes have no effect.
12-0 FIDXS 0-1FFFh Source address frame index. These bits define the offset to be added to the source address
after element count reached one.
767
SPNU562–May 2014 Direct Memory Access Controller (DMA) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated