Datasheet

Control Registers and Control Packets

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20.3.2 Channel Configuration

The channel configuration is defined by the channel control packet: channel control, transfer count, index

pointers, source/destination address.

• It is stored in local RAM, which is protected by parity.

• Each control packet contains a total of nine fields.

• The first six fields are programmable, while the last three fields are read only.

• The RAM is accessible by queue A and queue B state machines as well as CPU.

• When there are simultaneous accesses, the priority is resolved in a fixed priority scheme with the CPU

having the highest priority.

All the control packets look the same. Following, there is the detailed layout of these registers shown for

control packet 0.

20.3.2.1 Initial Source Address Register (ISADDR)

Figure 20-114. Initial Source Address Register (ISADDR) [offset = 00]

31 0

ISADDR

R/WP-X

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; X = Unknown

Table 20-102. Initial Source Address Register (ISADDR) Field Descriptions

Bit Field Description

31-0 ISADDR Initial source address. These bits give the absolute 32-bit source address (physical).

20.3.2.2 Initial Destination Address Register (IDADDR)

Figure 20-115. Initial Destination Address Register (IDADDR) [offset = 04h]

31 0

IDADDR

R/WP-X

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; X = Unknown

Table 20-103. Initial Destination Address Register (IDADDR) Field Descriptions

Bit Field Description

31-0 IDADDR Initial destination address. These bits give the absolute 32-bit destination address (physical).

764

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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