Datasheet

www.ti.com Control Registers and Control Packets
20.3.1.91 DMA Request Polarity Select Register 1 (DMAREQPS1)
Figure 20-109. DMA Request Polarity Select Register (DMAREQPS1) [offset = 330h]
31 0
DMAREQPS[63:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-97. DMA Request Polarity Select Register (DMAREQPS1) Field Descriptions
Bit Field Value Description
31-0 DMAREQOS[n] Polarity selection for DMA request lines for upper 32 requests, that is, request lines 63 to 32. Bit 0
corresponds to DMA Request line 32, bit 1 corresponds to DMA Request line 33, and so on.
0 DMA Request polarity is active high.
1 DMA Request polarity is active low.
20.3.1.92 DMA Request Polarity Select Register 0 (DMAREQPS0)
Figure 20-110. DMA Request Polarity Select Register (DMAREQPS0) [offset = 334h]
31 0
DMAREQPS[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-98. DMA Request Polarity Select Register (DMAREQPS1) Field Descriptions
Bit Field Value Description
31-0 DMAREQOS[n] Polarity selection for DMA request lines for lower 32 requests, that is, request lines 31 to 0. Bit 0
corresponds to DMA Request line 0, bit 1 corresponds to DMA Request line 1, and so on.
0 DMA Request polarity is active high.
1 DMA Request polarity is active low.
761
SPNU562–May 2014 Direct Memory Access Controller (DMA) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated