Datasheet

Control Registers and Control Packets

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20.3.1.89 FIFO A Status Register (FIFOASTAT)

Figure 20-107. FIFO A Status Register (FIFOASTAT) [offset = 240h]

31 0

FFACH[31:0]

R-0

LEGEND: R = Read only; -n = value after reset

Table 20-95. FIFO A Status Register (FIFOASTAT) Field Descriptions

Bit Field Value Description

31-0 FFACH[n] Status of DMA channel running using FIFO A. Bit 0 corresponds to channel 0, bit 1 corresponds to

channel 1, and so on.

0 The channel is not being currently processed.

1 The channel is currently being processed using FIFO A

Note: The status of a channel currently being processed remains active even if emulation mode is

entered or DMA is disabled via DMA_EN bit. Up to 1 bit can be set in this register at any given time.

20.3.1.90 FIFO B Status Register (FIFOBSTAT)

Figure 20-108. FIFO B Status Register (FIFOBSTAT) [offset = 244h]

31 0

FFBCH[31:0]

R-0

LEGEND: R = Read only; -n = value after reset

Table 20-96. FIFO B Status Register (FIFOBSTAT) Field Descriptions

Bit Field Value Description

31-0 FFBCH[n] Status of DMA channel running using FIFO B. Bit 0 corresponds to channel 0, bit 1 corresponds to

channel 1, and so on.

0 The channel is not being currently processed.

1 The channel is currently being processed using FIFO B

Note: The status of a channel currently being processed remains active even if emulation mode is

entered or DMA is disabled via DMA_EN bit. Up to 1 bit can be set in this register at any given time.

760

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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