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Control Registers and Control Packets

20.3.1.88 DMA ECC Single Bit Error Address Register (DMAECCSBE)

Figure 20-106. DMA ECC Single Bit Error Address Register (DMAECCSBE) [offset = 230h]

31 16

Reserved

R-0

15 12 11 0

Reserved ERRORADDRESS

R-0 R-X

LEGEND: R/W = Read/Write; R = Read only; X= Undefined; -n = value after reset

Table 20-94. DMA ECC Single Bit Error Address Register (DMAECCSBE) Field Descriptions

Bit Field Value Description

31-12 Reserved 0 Read returns 0. Writes have no effect.

11-0 ERRORADDRESS 0-FFFh The DMA RAM address (offset from base address word aligned) of the ECC error location.

This register gives the address of the first encountered single bit ECC error since the SBERR

flag has been clear. Subsequent single bit ECC errors will not update this register until the

SBERR flag has been cleared. This register is valid only when the SBERR flag is set.

Read: This register clears to 0x0000 once it is read by the CPU. For a read issued by the

debugger this address is frozen even when read.

Write: No effect

Note: The error address register will not be reset by PORRST nor by any other reset

source.

759

SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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