Datasheet

Control Registers and Control Packets

www.ti.com

20.3.1.87 DMA Single Bit ECC Control Register (DMASECCCTRL)

Figure 20-105. DMA Single Bit ECC Control Register (DMASECCCTRL) [offset = 228h]

31 17 16

Reserved SBERR

R-0 R/WCP-0

15 12 11 8 7 4 3 0

Reserved SBE_EVT_EN Reserved EDACMODE

R-0 R/WP-5h R-0 R/WP-Ah

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20-93. DMA Single Bit ECC Control Register (DMASECCCTRL) Field Description

Bit Field Value Description

31-17 Reserved 0 Read returns 0. Writes have no effect.

16 SBERR Error action.

0 Read and write: No RAM check error has occurred.

1 Read: A single bit error has occurred and was corrected by the SECDED logic.

Write: Clears the SBERR flag.

15-12 Reserved 0 Read returns 0. Writes have no effect.

11-8 SBE_EVT_EN Single bit error enable.

5h Disable generation of single bit error to ESM.

Ah Enable generation of single bit error to ESM.

7-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 EDACMODE 5h Disable correction of SBE detected by the SECDED block.

Ah Enable correction of SBE detected by the SECDED block.

758

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

Submit Documentation Feedback