Datasheet

98
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 6-28. CPU Interconnect Subsystem SDC Register Bit Field Mapping
Register name bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 Remark
ERR_GENERIC_PARITY PS_SCR_M POM DMA_PORTA Reserved CPU AXI-M ACP-M Reserved
• Each bit indicates the
transaction processing block
inside the interconnect
corresponding to the master
that is detected by the
interconnect checker to have
a fault.
• error related to parity
mismatch in the incoming
address
ERR_UNEXPECTED_TRANS PS_SCR_M POM DMA_PORTA Reserved CPU AXI-M ACP-M Reserved
• error related to unexpected
transaction sent by the
master
ERR_TRANS_ID PS_SCR_M POM DMA_PORTA Reserved CPU AXI-M ACP-M Reserved
• error related to mismatch on
the transaction ID
ERR_TRANS_SIGNATURE PS_SCR_M POM DMA_PORTA Reserved CPU AXI-M ACP-M Reserved
• error related to mismatch on
the transaction signature
ERR_TRANS_TYPE PS_SCR_M POM DMA_PORTA Reserved CPU AXI-M ACP-M Reserved
• error related to mismatch on
the transaction type
ERR_USER_PARITY PS_SCR_M POM DMA_PORTA Reserved CPU AXI-M ACP-M Reserved
• error related to mismatch on
the parity
SERR_UNEXPECTED_MID L2 RAM Wrapper
L2 Flash
Wrapper Port A
L2 Flash Wrapper
Port B
EMIF Reserved CPU AXi-S ACP-S
• Each bit indicates the
transaction processing block
inside the interconnect
corresponding to the slave
that is detected by the
interconnect checker to have
a fault.
• error related to mismatch on
the master ID
SERR_ADDR_DECODE L2 RAM Wrapper
L2 Flash
Wrapper Port A
L2 Flash Wrapper
Port B
EMIF Reserved CPU AXi-S ACP-S
• error related to mismatch on
the most significant address
bits
SERR_USER_PARITY L2 RAM Wrapper
L2 Flash
Wrapper Port A
L2 Flash Wrapper
Port B
EMIF Reserved CPU AXi-S ACP-S
• error related to mismatch on
the parity of the most
significant address bits