Datasheet
Control Registers and Control Packets
www.ti.com
20.3.1.79 DMA Memory Protection Region 4 Start Address Register (DMAMPR4S)
Figure 20-97. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) [offset =
1E0h]
31 0
STARTADDRESS
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-85. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) Field
Descriptions
Bit Field Description
31-0 STARTADDRESS Start Address defines the address at which the region begins.
20.3.1.80 DMA Memory Protection Region 4 End Address Register (DMAMPR4E)
Figure 20-98. DMA Memory Protection Region 4 End Address Register (DMAMPR4E) [offset =
1E4h]
31 0
ENDADDRESS
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-86. DMA Memory Protection Region 4 End Address Register (DMAMPR4E)] Field
Descriptions
Bit Field Description
31-0 ENDADDRESS End Address defines the address at which the region ends. The end address usually is larger than the
start address for this region; otherwise, the region will wrap around at the end of the address space.
754
Direct Memory Access Controller (DMA) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated