Datasheet

ID Decode Addr Decode

MasterID Address/Control

MasterID Protection Register N

Peripheral Select N

PCRx

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bit MasterID access protection register is defined. Each bit grants or denies the permission of the

corresponding binary coded decimal MasterID. For example, if bit 5 of the access permission register is

set, it grants MasterID 5 to access the peripheral. If bit 7 is clear, it denies MasterID 7 to access the

peripheral. Figure 6-10 shows the MasterID filtering scheme. Table 6-27 lists the MasterID of each master,

which can access the PCRx.

Figure 6-10. PCR MasterID Filtering

6.9.6 CPU Interconnect Subsystem SDC MMR Port

The CPU Interconnect Subsystem SDC MMR Port is a special slave to the Peripheral Interconnect

Subsystem. It is memory mapped at starting address of 0xFA00_0000. Various status registers pertaining

to the diagnostics of the CPU Interconnect Subsystem can be access through this slave port. The CPU

Interconnect Subsystem contains built-in hardware diagnostic checkers which will constantly watch

transactions flowing through the interconnect. There is a checker for each master and slave attached to

the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated

behavior by the interconnect. For example, if the CPU issues a burst read request to the flash, the

checker will ensure that the expected behavior is indeed a burst read request to the proper slave module.

If the interconnects generates a transaction which is not a read, or not a burst or not to the flash as the

destination, then the checker will flag it one of the registers. The detected error will also be signaled to the

ESM module. Refer to the Interconnect chapter of the TRM SPNU562 for details on the registers.