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Control Registers and Control Packets

20.3.1.66 DMA ECC Error Address Register (DMAPAR)

Figure 20-84. DMA ECC Error Address Register (DMAPAR) [offset = 1ACh]

31 25 24 23 16

Reserved EDFLAG Reserved

R-0 R-0 R-0

15 12 11 0

Reserved ERRORADDRESS

R-0 R-X

LEGEND: R/W = Read/Write; R = Read only; X= Undefined; -n = value after reset

Table 20-72. DMA ECC Error Address Register (DMAPAR) Field Descriptions

Bit Field Value Description

31-25 Reserved 0 Read returns 0. Writes have no effect.

24 EDFLAG ECC Error Detection Flag. This flag indicates if an ECC error occurred on reading DMA Control

packet RAM.

0 Read: No error occurred.

Write: No effect.

1 Read: Error detected and the address is captured in DMAPAR's ERROR_ADDRESS field

Write: Clears the bit.

23-12 Reserved 0 Read returns 0. Writes have no effect.

11-0 ERRORADDRESS 0-FFFh Error address. These bits hold the address of the first ECC error generated in the RAM. This

error address is frozen from being updated until it is read by the CPU. During emulation mode

when SUSPEND is high, this address is frozen even when read.

Note: The error address register will not be reset by PORRST nor by any other reset

source.

743

SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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