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Control Registers and Control Packets

20.3.1.57 Watch Point Register (WPR)

Figure 20-75. Watch Point Register (WPR) [offset = 184h]

31 0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 20-63. Watch Point Register (WPR) Field Descriptions

Bit Field Description

31-0 WP Watch point.

Note: These bits can only be set when using a debugger.

This register is only reset by a test reset (nTRST). A 32-bit address can be programmed into this register as a

watch point. This register is used with the watch mask register (WMR).

When the DBGEN bit in the DCTRL register is set and a unique address or a range of addresses are detected

on the AHB address bus of Port B, a debug request signal is sent to the ARM CPU. The state machine of the

port in which the watch point condition is true is frozen.

20.3.1.58 Watch Mask Register (WMR)

Figure 20-76. Watch Mask Register (WMR) [offset = 188h]

31 0

WM[31:0]

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 20-64. Watch Mask Register (WMR) Field Descriptions

Bit Field Value Description

31-0 WM[n] Watch mask.

Note: These bits can only be set when using a debugger.

This register is only reset by a test reset (nTRST).

0 Setting a bit to 0 allows the bit in the WPR register to be used for address matching for a watch point.

1 Setting a bit to 1 in the WMR register masks the corresponding bit in the WPR register and is

disregarded in the comparison.

739

SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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