Datasheet

Control Registers and Control Packets

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20.3.1.56 Debug Control Register (DCTRL)

Figure 20-74. Debug Control Register (DCTRL) [offset = 180h]

31 29 28 24 23 17 16

Reserved CHNUM Reserved DMADBGS

R-0 R-0 R-0 R/WC-0

15 1 0

Reserved DBGEN

R-0 R/WC-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 20-62. Debug Control Register (DCTRL) Field Descriptions

Bit Field Value Description

31-29 Reserved 0 Read returns 0. Writes have no effect.

28-24 CHNUM 0-1Fh Channel Number. This bit field indicates the channel number that causes the watch point to match.

23-17 Reserved 0 Read returns 0. Writes have no effect.

16 DMADBGS DMA debug status. When a watch point is set up to watch for a unique bus address or a range of

addresses is true on one of the three bus ports, then the DMA debug status bit is set to 1 and a

debug request signal is asserted to the main CPU. The CPU must write a 1 to clear this bit for the

DMA controller to release the debug request signal.

0 Read: No watch point condition is detected.

Write: No effect.

1 Read: The watch point condition is detected.

Write: The bit is cleared.

15-1 Reserved 0 Read returns 0. Writes have no effect.

0 DBGEN Debug Enable.

Note: This bit can only be set when using a debugger.

Note: This bit is reset when Test reset (nTRST) is low.

0 Debug is disabled.

1 The watch point checking logics is enabled.

738

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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