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Control Registers and Control Packets

20.3.1.55 RAM Test Control Register (RTCTRL)

Figure 20-73. RAM Test Control Register (RTCTRL) [offset = 17Ch]

31 16

Reserved

R-0

15 1 0

Reserved RTC

R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 20-61. RAM Test Control Register (RTCTRL) Field Descriptions

Bit Field Value Description

31-1 Reserved 0 Read returns 0. Writes have no effect.

0 RTC RAM Test Control. Writing a 1 to this bit opens the write access to the reserved locations of control

packet RAM as defined in the memory map.

Note: This bit should be set to zero during normal operation.

0 RAM Test Control Disabled.

1 RAM Test Control Enabled..

737

SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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