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Control Registers and Control Packets

20.3.1.52 BTCB Interrupt Channel Offset Register (BTCBOFFSET)

Figure 20-70. BTCB Interrupt Channel Offset Register (BTCBOFFSET) [offset = 16Ch]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz BTCB

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-58. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 BTCB Channel causing BTC interrupt Group B. These bits contain the channel number of the pending

interrupt for Group B if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.42) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group B.

: :

20h Channel 31 is causing the pending interrupt Group B.

20.3.1.53 BERB Interrupt Channel Offset Register (BERBOFFSET)

Figure 20-71. BERB Interrupt Channel Offset Register (BERBOFFSET) [offset = 170h]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz BERB

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-59. BERB Interrupt Channel Offset Register (BERBOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 BERB Channel causing BER interrupt Group B. These bits contain the channel number of the pending

interrupt for Group B if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.43) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group B.

: :

20h Channel 31 is causing the pending interrupt Group B.

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SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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