Datasheet

96
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.9.4 Master/Slave Access Privileges
Table 6-26 and Table 6-27 list the access permissions for each bus master on the device. A bus master is
a module that can initiate a read or a write transaction on the device.
Each slave module on either the CPU Interconnect Subsystem or the Peripheral Interconnect Subsystem
is listed in Table 6-27. Allowed indicates that the module listed in the MASTERS column can access that
slave module.
Table 6-26. Bus Master / Slave Access Matrix for CPU Interconnect Subsystem
MASTERS
SLAVES ON CPU INTERCONNECT SUBSYSTEM
L2 Flash OTP, ECC,
Bank 7 (EEPROM)
L2 FLASH L2 SRAM CACHE MEMORY EMIF
CPU Read Allowed Allowed Allowed Allowed Allowed
CPU Write Not allowed Not allowed Allowed Allowed Allowed
DMA PortA Allowed Allowed Allowed Not allowed Allowed
POM Not allowed Not allowed Allowed Not allowed Allowed
PS_SCR_M Allowed Allowed Allowed Not allowed Allowed
ACP_M Not allowed Not Allowed Allowed Not allowed Not allowed
Table 6-27. Bus Master / Slave Access Matrix for Peripheral Interconnect Subsystem
MASTER ID TO
PCRx
MASTERS
SLAVES ON PERIPHERAL INTERCONNECT SUBSYSTEM
CRC1/CRC2
Resources Under
PCR2 and PCR3
Resources Under
PCR1
CPU Interconnect
Subsystem SDC
MMR Port (see
Section 6.9.6 )
0
CPU Read Allowed Allowed Allowed Allowed
CPU Write Allowed Allowed Allowed Allowed
1 Reserved – – – –
2 DMA PortB Allowed Allowed Allowed Not allowed
3 HTU1 Not allowed Not allowed Not allowed Not allowed
4 HTU2 Not allowed Not allowed Not allowed Not allowed
7 DMM Allowed Allowed Allowed Allowed
9 DAP Allowed Allowed Allowed Allowed
10 EMAC Not allowed Allowed Not allowed Not allowed
6.9.4.1 Special Notes on Accesses to Certain Slaves
By design only the CPU and debugger can have privileged write access to peripherals under the PCR1
segment. The other masters can only read from these registers.
The master-id filtering check is implemented inside each PCR module of each peripheral segment and
can be used to block certain masters from write accesses to certain peripherals. An unauthorized master
write access detected by the PCR will result in the transaction being discarded and an error being
generated to the ESM module.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned off.
6.9.5 MasterID to PCRx
The MasterID associated with each master port on the Peripheral Interconnect Subsystem contains a 4-bit
value. The MasterID is passed along with the address and control signals to three PCR modules. PCR
decodes the address and control signals to select the peripheral. In addition, it decodes this 4-bit MasterID
value to perform memory protection. With 4-bit of MasterID, it allows the PCR to distinguish among 16
different masters to allow or disallow access to a given peripheral. Associated with each peripheral a 16-