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Control Registers and Control Packets

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20.3.1.50 LFSB Interrupt Channel Offset Register (LFSBOFFSET)

Figure 20-68. LFSB Interrupt Channel Offset Register (LFSBOFFSET) [offset = 164h]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz LFSB

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-56. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 LFSB Channel causing LFS interrupt Group B. These bits contain the channel number of the pending interrupt

for Group B if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.40) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group B.

: :

20h Channel 31 is causing the pending interrupt Group B.

20.3.1.51 HBCB Interrupt Channel Offset Register (HBCBOFFSET)

Figure 20-69. HBCB Interrupt Channel Offset Register (HBCBOFFSET) [offset = 168h]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz HBCB

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-57. HBCB Interrupt Channel Offset Register (HBCBOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 HBCB Channel causing HBC interrupt Group B. These bits contain the channel number of the pending

interrupt for Group B if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.41) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group B.

: :

20h Channel 31 is causing the pending interrupt Group B.

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Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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