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Control Registers and Control Packets

20.3.1.48 BERA Interrupt Channel Offset Register (BERAOFFSET)

Figure 20-66. BERA Interrupt Channel Offset Register (BERAOFFSET) [offset = 15Ch]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz BERA

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-54. BERA Interrupt Channel Offset Register (BERAOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 BERA Channel causing BER interrupt Group A. These bits contain the channel number of the pending

interrupt for Group A if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.43) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group A.

: :

20h Channel 31 is causing the pending interrupt Group A.

20.3.1.49 FTCB Interrupt Channel Offset Register (FTCBOFFSET)

Figure 20-67. FTCB Interrupt Channel Offset Register (FTCBOFFSET) [offset = 160h]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz FTCB

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-55. FTCB Interrupt Channel Offset Register (FTCBOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 FTCB Channel causing FTC interrupt Group B. These bits contain the channel number of the pending interrupt

for Group B if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.39) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group B.

: :

20h Channel 31 is causing the pending interrupt Group B.

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SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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